Vladimir requested support so we can at least load r300 microcode for

    helping
2D operations.
Ups radeon to version 1.12.0, Vladimir, you might want to add any extra
    pciids...
Approved-by: Dave Airlie <airlied@linux.ie>

diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt
index 626d5a7..0ec9e7e 100644 (file)
--- a/shared-core/drm_pciids.txt
+++ b/shared-core/drm_pciids.txt
@@ -19,6 +19,7 @@
 0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
 0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
 0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
+0x1002 0x4E50 CHIP_RV350 | CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10"
 0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
 0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
 0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 36a77ad..96e6d65 100644 (file)
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -554,6 +554,265 @@ static u32 radeon_cp_microcode[][2] = {
        {0000000000, 0000000000},
 };
 
+static u32 R300_cp_microcode[][2] = {
+       { 0x4200e000, 0000000000 },
+       { 0x4000e000, 0000000000 },
+       { 0x000000af, 0x00000008 },
+       { 0x000000b3, 0x00000008 },
+       { 0x6c5a504f, 0000000000 },
+       { 0x4f4f497a, 0000000000 },
+       { 0x5a578288, 0000000000 },
+       { 0x4f91906a, 0000000000 },
+       { 0x4f4f4f4f, 0000000000 },
+       { 0x4fe24f44, 0000000000 },
+       { 0x4f9c9c9c, 0000000000 },
+       { 0xdc4f4fde, 0000000000 },
+       { 0xa1cd4f4f, 0000000000 },
+       { 0xd29d9d9d, 0000000000 },
+       { 0x4f0f9fd7, 0000000000 },
+       { 0x000ca000, 0x00000004 },
+       { 0x000d0012, 0x00000038 },
+       { 0x0000e8b4, 0x00000004 },
+       { 0x000d0014, 0x00000038 },
+       { 0x0000e8b6, 0x00000004 },
+       { 0x000d0016, 0x00000038 },
+       { 0x0000e854, 0x00000004 },
+       { 0x000d0018, 0x00000038 },
+       { 0x0000e855, 0x00000004 },
+       { 0x000d001a, 0x00000038 },
+       { 0x0000e856, 0x00000004 },
+       { 0x000d001c, 0x00000038 },
+       { 0x0000e857, 0x00000004 },
+       { 0x000d001e, 0x00000038 },
+       { 0x0000e824, 0x00000004 },
+       { 0x000d0020, 0x00000038 },
+       { 0x0000e825, 0x00000004 },
+       { 0x000d0022, 0x00000038 },
+       { 0x0000e830, 0x00000004 },
+       { 0x000d0024, 0x00000038 },
+       { 0x0000f0c0, 0x00000004 },
+       { 0x000d0026, 0x00000038 },
+       { 0x0000f0c1, 0x00000004 },
+       { 0x000d0028, 0x00000038 },
+       { 0x0000f041, 0x00000004 },
+       { 0x000d002a, 0x00000038 },
+       { 0x0000f184, 0x00000004 },
+       { 0x000d002c, 0x00000038 },
+       { 0x0000f185, 0x00000004 },
+       { 0x000d002e, 0x00000038 },
+       { 0x0000f186, 0x00000004 },
+       { 0x000d0030, 0x00000038 },
+       { 0x0000f187, 0x00000004 },
+       { 0x000d0032, 0x00000038 },
+       { 0x0000f180, 0x00000004 },
+       { 0x000d0034, 0x00000038 },
+       { 0x0000f393, 0x00000004 },
+       { 0x000d0036, 0x00000038 },
+       { 0x0000f38a, 0x00000004 },
+       { 0x000d0038, 0x00000038 },
+       { 0x0000f38e, 0x00000004 },
+       { 0x0000e821, 0x00000004 },
+       { 0x0140a000, 0x00000004 },
+       { 0x00000043, 0x00000018 },
+       { 0x00cce800, 0x00000004 },
+       { 0x001b0001, 0x00000004 },
+       { 0x08004800, 0x00000004 },
+       { 0x001b0001, 0x00000004 },
+       { 0x08004800, 0x00000004 },
+       { 0x001b0001, 0x00000004 },
+       { 0x08004800, 0x00000004 },
+       { 0x0000003a, 0x00000008 },
+       { 0x0000a000, 0000000000 },
+       { 0x02c0a000, 0x00000004 },
+       { 0x000ca000, 0x00000004 },
+       { 0x00130000, 0x00000004 },
+       { 0x000c2000, 0x00000004 },
+       { 0xc980c045, 0x00000008 },
+       { 0x2000451d, 0x00000004 },
+       { 0x0000e580, 0x00000004 },
+       { 0x000ce581, 0x00000004 },
+       { 0x08004580, 0x00000004 },
+       { 0x000ce581, 0x00000004 },
+       { 0x0000004c, 0x00000008 },
+       { 0x0000a000, 0000000000 },
+       { 0x000c2000, 0x00000004 },
+       { 0x0000e50e, 0x00000004 },
+       { 0x00032000, 0x00000004 },
+       { 0x00022056, 0x00000028 },
+       { 0x00000056, 0x00000024 },
+       { 0x0800450f, 0x00000004 },
+       { 0x0000a050, 0x00000008 },
+       { 0x0000e565, 0x00000004 },
+       { 0x0000e566, 0x00000004 },
+       { 0x00000057, 0x00000008 },
+       { 0x03cca5b4, 0x00000004 },
+       { 0x05432000, 0x00000004 },
+       { 0x00022000, 0x00000004 },
+       { 0x4ccce063, 0x00000030 },
+       { 0x08274565, 0x00000004 },
+       { 0x00000063, 0x00000030 },
+       { 0x08004564, 0x00000004 },
+       { 0x0000e566, 0x00000004 },
+       { 0x0000005a, 0x00000008 },
+       { 0x00802066, 0x00000010 },
+       { 0x00202000, 0x00000004 },
+       { 0x001b00ff, 0x00000004 },
+       { 0x01000069, 0x00000010 },
+       { 0x001f2000, 0x00000004 },
+       { 0x001c00ff, 0x00000004 },
+       { 0000000000, 0x0000000c },
+       { 0x00000085, 0x00000030 },
+       { 0x0000005a, 0x00000008 },
+       { 0x0000e576, 0x00000004 },
+       { 0x000ca000, 0x00000004 },
+       { 0x00012000, 0x00000004 },
+       { 0x00082000, 0x00000004 },
+       { 0x1800650e, 0x00000004 },
+       { 0x00092000, 0x00000004 },
+       { 0x000a2000, 0x00000004 },
+       { 0x000f0000, 0x00000004 },
+       { 0x00400000, 0x00000004 },
+       { 0x00000079, 0x00000018 },
+       { 0x0000e563, 0x00000004 },
+       { 0x00c0e5f9, 0x000000c2 },
+       { 0x0000006e, 0x00000008 },
+       { 0x0000a06e, 0x00000008 },
+       { 0x0000e576, 0x00000004 },
+       { 0x0000e577, 0x00000004 },
+       { 0x0000e50e, 0x00000004 },
+       { 0x0000e50f, 0x00000004 },
+       { 0x0140a000, 0x00000004 },
+       { 0x0000007c, 0x00000018 },
+       { 0x00c0e5f9, 0x000000c2 },
+       { 0x0000007c, 0x00000008 },
+       { 0x0014e50e, 0x00000004 },
+       { 0x0040e50f, 0x00000004 },
+       { 0x00c0007f, 0x00000008 },
+       { 0x0000e570, 0x00000004 },
+       { 0x0000e571, 0x00000004 },
+       { 0x0000e572, 0x0000000c },
+       { 0x0000a000, 0x00000004 },
+       { 0x0140a000, 0x00000004 }, 
+       { 0x0000e568, 0x00000004 },
+       { 0x000c2000, 0x00000004 },
+       { 0x00000089, 0x00000018 },
+       { 0x000b0000, 0x00000004 },
+       { 0x18c0e562, 0x00000004 },
+       { 0x0000008b, 0x00000008 },
+       { 0x00c0008a, 0x00000008 },
+       { 0x000700e4, 0x00000004 },
+       { 0x00000097, 0x00000038 },
+       { 0x000ca099, 0x00000030 },
+       { 0x080045bb, 0x00000004 },
+       { 0x000c209a, 0x00000030 },
+       { 0x0800e5bc, 0000000000 },
+       { 0x0000e5bb, 0x00000004 },
+       { 0x0000e5bc, 0000000000 },
+       { 0x00120000, 0x0000000c },
+       { 0x00120000, 0x00000004 },
+       { 0x001b0002, 0x0000000c },
+       { 0x0000a000, 0x00000004 },
+       { 0x0000e821, 0x00000004 },
+       { 0x0000e800, 0000000000 },
+       { 0x0000e821, 0x00000004 },
+       { 0x0000e82e, 0000000000 },
+       { 0x02cca000, 0x00000004 },
+       { 0x00140000, 0x00000004 },
+       { 0x000ce1cc, 0x00000004 },
+       { 0x050de1cd, 0x00000004 },
+       { 0x000000a7, 0x00000020 },
+       { 0x4200e000, 0000000000 },
+       { 0x000000ae, 0x00000038 },
+       { 0x000ca000, 0x00000004 },
+       { 0x00140000, 0x00000004 },
+       { 0x000c2000, 0x00000004 },
+       { 0x00160000, 0x00000004 },
+       { 0x700ce000, 0x00000004 },
+       { 0x001400aa, 0x00000008 },
+       { 0x4000e000, 0000000000 },
+       { 0x02400000, 0x00000004 },
+       { 0x400ee000, 0x00000004 },
+       { 0x02400000, 0x00000004 },
+       { 0x4000e000, 0000000000 },
+       { 0x000c2000, 0x00000004 },
+       { 0x0240e51b, 0x00000004 },
+       { 0x0080e50a, 0x00000005 },
+       { 0x0080e50b, 0x00000005 },
+       { 0x00220000, 0x00000004 },
+       { 0x000700e4, 0x00000004 },
+       { 0x000000c1, 0x00000038 },
+       { 0x000c209a, 0x00000030 },
+       { 0x0880e5bd, 0x00000005 },
+       { 0x000c2099, 0x00000030 },
+       { 0x0800e5bb, 0x00000005 },
+       { 0x000c209a, 0x00000030 },
+       { 0x0880e5bc, 0x00000005 },
+       { 0x000000c4, 0x00000008 },
+       { 0x0080e5bd, 0x00000005 },
+       { 0x0000e5bb, 0x00000005 },
+       { 0x0080e5bc, 0x00000005 },
+       { 0x00210000, 0x00000004 },
+       { 0x02800000, 0x00000004 },
+       { 0x00c000c8, 0x00000018 },
+       { 0x4180e000, 0x00000040 },
+       { 0x000000ca, 0x00000024 },
+       { 0x01000000, 0x0000000c },
+       { 0x0100e51d, 0x0000000c },
+       { 0x000045bb, 0x00000004 },
+       { 0x000080c4, 0x00000008 },
+       { 0x0000f3ce, 0x00000004 },
+       { 0x0140a000, 0x00000004 },
+       { 0x00cc2000, 0x00000004 },
+       { 0x08c053cf, 0x00000040 },
+       { 0x00008000, 0000000000 },
+       { 0x0000f3d2, 0x00000004 },
+       { 0x0140a000, 0x00000004 },
+       { 0x00cc2000, 0x00000004 },
+       { 0x08c053d3, 0x00000040 },
+       { 0x00008000, 0000000000 },
+       { 0x0000f39d, 0x00000004 },
+       { 0x0140a000, 0x00000004 },
+       { 0x00cc2000, 0x00000004 },
+       { 0x08c0539e, 0x00000040 },
+       { 0x00008000, 0000000000 },
+       { 0x03c00830, 0x00000004 },
+       { 0x4200e000, 0000000000 },
+       { 0x0000a000, 0x00000004 },
+       { 0x200045e0, 0x00000004 },
+       { 0x0000e5e1, 0000000000 },
+       { 0x00000001, 0000000000 },
+       { 0x000700e1, 0x00000004 },
+       { 0x0800e394, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+       { 0000000000, 0000000000 },
+};
+
 int RADEON_READ_PLL(drm_device_t * dev, int addr)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -676,7 +935,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 
        RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 
-       if (dev_priv->is_r200) {
+       if (dev_priv->microcode_version==UCODE_R200) {
                DRM_INFO("Loading R200 Microcode\n");
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -684,6 +943,14 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                     R200_cp_microcode[i][0]);
                }
+       } else if (dev_priv->microcode_version==UCODE_R300) {
+               DRM_INFO("Loading R300 Microcode\n");
+               for ( i = 0 ; i < 256 ; i++ ) {
+                       RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
+                                     R300_cp_microcode[i][1] );
+                       RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
+                                     R300_cp_microcode[i][0] );
+               }
        } else {
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1010,7 +1277,18 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
                return DRM_ERR(EINVAL);
        }
 
-       dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
+       switch(init->func) {
+       case RADEON_INIT_R200_CP:
+               dev_priv->microcode_version=UCODE_R200;
+               break;
+       case RADEON_INIT_R300_CP:
+               dev_priv->microcode_version=UCODE_R300;
+               break;
+       default:
+               dev_priv->microcode_version=UCODE_R100;
+               break;
+       }
+
        dev_priv->do_boxes = 0;
        dev_priv->cp_mode = init->cp_mode;
 
@@ -1328,6 +1606,7 @@ int radeon_cp_init(DRM_IOCTL_ARGS)
        switch (init.func) {
        case RADEON_INIT_CP:
        case RADEON_INIT_R200_CP:
+       case RADEON_INIT_R300_CP:
                return radeon_do_init_cp(dev, &init);
        case RADEON_CLEANUP_CP:
                return radeon_do_cleanup_cp(dev);

diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index 4b161cf..7c60093 100644 (file)
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -423,7 +423,8 @@ typedef struct drm_radeon_init {
        enum {
                RADEON_INIT_CP = 0x01,
                RADEON_CLEANUP_CP = 0x02,
-               RADEON_INIT_R200_CP = 0x03
+               RADEON_INIT_R200_CP = 0x03,
+               RADEON_INIT_R300_CP = 0x04
        } func;
        unsigned long sarea_priv_offset;
        int is_pci;             /* not used, driver asks hardware */

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 6d96cf5..3c7a6fe 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -40,8 +40,44 @@
 #define DRIVER_DESC            "ATI Radeon"
 #define DRIVER_DATE            "20020828"
 
+/* Interface history:
+ *
+ * 1.1 - ??
+ * 1.2 - Add vertex2 ioctl (keith)
+ *     - Add stencil capability to clear ioctl (gareth, keith)
+ *     - Increase MAX_TEXTURE_LEVELS (brian)
+ * 1.3 - Add cmdbuf ioctl (keith)
+ *     - Add support for new radeon packets (keith)
+ *     - Add getparam ioctl (keith)
+ *     - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
+ * 1.4 - Add scratch registers to get_param ioctl.
+ * 1.5 - Add r200 packets to cmdbuf ioctl
+ *     - Add r200 function to init ioctl
+ *     - Add 'scalar2' instruction to cmdbuf
+ * 1.6 - Add static GART memory manager
+ *       Add irq handler (won't be turned on unless X server knows to)
+ *       Add irq ioctls and irq_active getparam.
+ *       Add wait command for cmdbuf ioctl
+ *       Add GART offset query for getparam
+ * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
+ *       and R200_PP_CUBIC_OFFSET_F1_[0..5].
+ *       Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
+ *       R200_EMIT_PP_CUBIC_OFFSETS_[0..5].  (brian)
+ * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
+ *       Add 'GET' queries for starting additional clients on different VT's.
+ * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
+ *       Add texture rectangle support for r100.
+ * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
+ *       clients use to tell the DRM where they think the framebuffer is
+ *       located in the card's address space
+ * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
+ *       and GL_EXT_blend_[func|equation]_separate on r200
+ * 1.12- Add R300 CP microcode support - this just loads the CP on r300
+ *       (No 3D support yet - just microcode loading).
+ */
+
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           11
+#define DRIVER_MINOR           12
 #define DRIVER_PATCHLEVEL      0
 
 enum radeon_family {
@@ -57,9 +93,16 @@ enum radeon_family {
        CHIP_RV280,
        CHIP_R300,
        CHIP_RS300,
+       CHIP_RV350,
        CHIP_LAST,
 };
 
+enum radeon_cp_microcode_version {
+       UCODE_R100,
+       UCODE_R200,
+       UCODE_R300,
+};
+
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
 #include "radeon_i2c.h"
 #endif
@@ -139,7 +182,7 @@ typedef struct drm_radeon_private {
 
        int usec_timeout;
 
-       int is_r200;
+       int microcode_version;
 
        unsigned long phys_pci_gart;
        dma_addr_t bus_pci_gart;

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 325ce07..1b69430 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -798,7 +798,7 @@ static void radeon_cp_dispatch_clear(drm_device_t * dev,
         * rendering a quad into just those buffers.  Thus, we have to
         * make sure the 3D engine is configured correctly.
         */
-       if (dev_priv->is_r200 && (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
+       if ((dev_priv->microcode_version == UCODE_R200) && (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
 
                int tempPP_CNTL;
                int tempRE_CNTL;