AARCH64_ARCH_EXT_NAME("sme", AArch64::AEK_SME, "+sme", "-sme")
AARCH64_ARCH_EXT_NAME("sme-f64", AArch64::AEK_SMEF64, "+sme-f64", "-sme-f64")
AARCH64_ARCH_EXT_NAME("sme-i64", AArch64::AEK_SMEI64, "+sme-i64", "-sme-i64")
+AARCH64_ARCH_EXT_NAME("sme2", AArch64::AEK_SME2, "+sme2", "-sme2")
AARCH64_ARCH_EXT_NAME("hbc", AArch64::AEK_HBC, "+hbc", "-hbc")
AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops", "-mops")
AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon")
AEK_HBC = 1ULL << 40, // FEAT_HBC
AEK_MOPS = 1ULL << 41, // FEAT_MOPS
AEK_PERFMON = 1ULL << 42, // FEAT_PMUv3
+ AEK_SME2 = 1ULL << 43, // FEAT_SME2
};
enum class ArchKind {
def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
"Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
+def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true",
+ "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
+
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
"Apple A7 (the CPU formerly known as Cyclone)">;
}
def SMEUnsupported : AArch64Unsupported {
- let F = [HasSME, HasSMEF64, HasSMEI64];
+ let F = [HasSME, HasSMEF64, HasSMEI64, HasSME2];
}
include "AArch64SchedA53.td"
AssemblerPredicateWithAll<(all_of FeatureSMEF64), "sme-f64">;
def HasSMEI64 : Predicate<"Subtarget->hasSMEI64()">,
AssemblerPredicateWithAll<(all_of FeatureSMEI64), "sme-i64">;
+def HasSME2 : Predicate<"Subtarget->hasSME2()">,
+ AssemblerPredicate<(all_of FeatureSME2), "sme2">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
def HasSVEorSME
list<Predicate> UnsupportedFeatures =
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
- HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16];
+ HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2];
let FullInstRWOverlapCheck = 0;
}
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
+ SMEUnsupported.F,
[HasMTE]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
--- /dev/null
+// This test verifies SME2 implies SME.
+
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s \
+// RUN: | FileCheck %s
+
+addha za0.s, p0/m, p0/m, z0.s
+// CHECK-NOT: instruction requires: sme
+// CHECK: addha za0.s, p0/m, p0/m, z0.s
AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64, AArch64::AEK_SMEI64,
- AArch64::AEK_HBC, AArch64::AEK_MOPS, AArch64::AEK_PERFMON};
+ AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
+ AArch64::AEK_PERFMON};
std::vector<StringRef> Features;
EXPECT_TRUE(llvm::is_contained(Features, "+sme"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-f64"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-i64"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sme2"));
EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
{"sme", "nosme", "+sme", "-sme"},
{"sme-f64", "nosme-f64", "+sme-f64", "-sme-f64"},
{"sme-i64", "nosme-i64", "+sme-i64", "-sme-i64"},
+ {"sme2", "nosme2", "+sme2", "-sme2"},
{"hbc", "nohbc", "+hbc", "-hbc"},
{"mops", "nomops", "+mops", "-mops"},
{"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},