ret = "mflo\t%0";
}
- else if (ST_REG_P (regno1) && mips_isa >= 4)
+ else if (ST_REG_P (regno1) && ISA_HAS_FP4)
ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
else
if (FP_REG_P (regno1))
ret = "mfc1\t%0,%1";
- else if (regno1 == FPSW_REGNUM && mips_isa < 4)
+ else if (regno1 == FPSW_REGNUM && ! ISA_HAS_FP4)
ret = "cfc1\t%0,$31";
}
}
}
}
- else if (regno0 == FPSW_REGNUM && mips_isa < 4)
+ else if (regno0 == FPSW_REGNUM && ! ISA_HAS_FP4)
{
if (GP_REG_P (regno1))
{
or higher. For !TARGET_64BIT && gp registers we
need to avoid this by using two li instructions
instead. */
- if (mips_isa >= 3 && !TARGET_64BIT && !FP_REG_P (regno0))
+ if (ISA_HAS_64BIT_REGS
+ && ! TARGET_64BIT
+ && ! FP_REG_P (regno0))
{
split_double (op1, operands + 2, operands + 3);
ret = "li\t%0,%2\n\tli\t%D0,%3";
case CMP_SF:
case CMP_DF:
- if (mips_isa < 4)
+ if (! ISA_HAS_FP4)
reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
else
reg = gen_reg_rtx (CCmode);
if (mips_abi_string == 0 && mips_isa_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
- if (mips_isa <= 2)
+ if (! ISA_HAS_64BIT_REGS)
mips_abi = ABI_32;
else
mips_abi = ABI_64;
/* If both ABI and ISA were specified, check for conflicts. */
else if (mips_isa_string && mips_abi_string)
{
- if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
+ if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
|| mips_abi == ABI_O64))
- || (mips_isa >= 3 && mips_abi == ABI_32))
+ || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
}
}
}
- if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
- || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
+ if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
+ || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
|| mips_cpu == PROCESSOR_R4600
|| mips_cpu == PROCESSOR_R4650)
- && mips_isa > 3))
+ && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
/* make sure sizes of ints/longs/etc. are ok */
- if (mips_isa < 3)
+ if (! ISA_HAS_64BIT_REGS)
{
if (TARGET_FLOAT64)
- fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
+ fatal ("-mips%d does not support 64 bit fp registers", mips_isa);
else if (TARGET_64BIT)
- fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
+ fatal ("-mips%d does not support 64 bit gp registers", mips_isa);
}
if (mips_abi != ABI_32 && mips_abi != ABI_O64)
if (mode == CCmode)
{
- if (mips_isa < 4)
+ if (! ISA_HAS_FP4)
temp = (regno == FPSW_REGNUM);
else
temp = (ST_REG_P (regno) || GP_REG_P (regno)
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"madd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"madd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"msub.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmadd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"nmadd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
(minus:DF (match_operand:DF 1 "register_operand" "f")
(mult:DF (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"nmsub.d\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
(minus:SF (match_operand:SF 1 "register_operand" "f")
(mult:SF (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"nmsub.s\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(match_operand:DF 2 "register_operand" "f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"recip.d\\t%0,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "DF")])
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(match_operand:SF 2 "register_operand" "f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_fast_math"
"recip.s\\t%0,%2"
[(set_attr "type" "fdiv")
(set_attr "mode" "SF")])
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
"rsqrt.d\\t%0,%2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "DF")])
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_fast_math"
"rsqrt.s\\t%0,%2"
[(set_attr "type" "fsqrt")
(set_attr "mode" "SF")])
(define_insn "movcc"
[(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"* return mips_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
(set_attr "mode" "SI")
[(set (match_operand:CC 0 "register_operand" "=z")
(match_operand:CC 1 "general_operand" "z"))
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"
{
rtx source;
[(set (match_operand:CC 0 "general_operand" "=z")
(match_operand:CC 1 "register_operand" "z"))
(clobber (match_operand:CC 2 "register_operand" "=&d"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"
{
/* This is called when we are copying a condition code register out
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "SF")])
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "SF")])
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "DF")])
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d"))))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\\t%0,%1(%2)"
[(set_attr "type" "load")
(set_attr "mode" "DF")])
[(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "SF")])
[(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "SF")])
[(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "DF")])
[(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\\t%0,%1(%2)"
[(set_attr "type" "store")
(set_attr "mode" "DF")])
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "ISA_HAS_CONDMOVE"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
(const_int 0)])
(match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%T3\\t%0,%z1,%4
mov%t3\\t%0,%z2,%4"
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
(const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%B4.s\\t%0,%2,%1
mov%b4.s\\t%0,%3,%1"
(const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"@
mov%T3.s\\t%0,%1,%4
mov%t3.s\\t%0,%2,%4"
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
(const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%B4.d\\t%0,%2,%1
mov%b4.d\\t%0,%3,%1"
(const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
mov%T3.d\\t%0,%1,%4
mov%t3.d\\t%0,%2,%4"
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
- "mips_isa >= 4"
+ "ISA_HAS_CONDMOVE || ISA_HAS_FP4"
"
{
gen_conditional_move (operands);
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
- "mips_isa >= 4"
+ "ISA_HAS_CONDMOVE || ISA_HAS_FP4"
"
{
gen_conditional_move (operands);
(if_then_else:SF (match_dup 5)
(match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "register_operand" "")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"
{
gen_conditional_move (operands);
(if_then_else:DF (match_dup 5)
(match_operand:DF 2 "register_operand" "")
(match_operand:DF 3 "register_operand" "")))]
- "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
gen_conditional_move (operands);