ARM: DTS: exynos5420: add GSCL block parent clock management to pm domain

Add support for restoring GSCALLER parent clocks configuration when GSCL
power domain is turned on.

Change-id: Id9e43306a59e930c6068e82bc55850dbb0440672
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8640896946693b48c66e75af53ee3926c3c0a602..cd9fc5bb411fb4125a0770ae4d9069e058484109 100644 (file)
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -299,8 +299,10 @@
                compatible = "samsung,exynos4210-pd";
                reg = <0x10044000 0x20>;
                #power-domain-cells = <0>;
-               clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>, <&clock CLK_FIMC_3AA>;
-               clock-names = "asb0", "asb1", "asb2";
+               clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>,
+                       <&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>,
+                       <&clock CLK_GSCL1>, <&clock CLK_FIMC_3AA>;
+               clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1", "asb2";
        };
 
        isp_pd: power-domain@10044020 {