AMDGPU: Document address space mapping

Summary:
Address space mapping is described in lib/Target/AMDGPU/AMDGPU.h in
Doxygen comments. This patch adds the description to user guide for
AMDGPU back-end.

Patch By: Vedran Miletić

Reviewers: tstellarAMD, arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17046

llvm-svn: 265500

diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 5abbdec..b5991c7 100644 (file)
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -9,6 +9,29 @@ The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
 the R600 family up until the current Volcanic Islands (GCN Gen 3).
 
 
+Conventions
+===========
+
+Address Spaces
+--------------
+
+The AMDGPU back-end uses the following address space mapping:
+
+   ============= ============================================
+   Address Space Memory Space
+   ============= ============================================
+   0             Private
+   1             Global
+   2             Constant
+   3             Local
+   4             Generic (Flat)
+   5             Region
+   ============= ============================================
+
+The terminology in the table, aside from the region memory space, is from the
+OpenCL standard.
+
+
 Assembler
 =========