*/
#include <common.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/system.h>
__weak int dram_init(void)
{
- initdram();
+ fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
}
#endif
-int initdram(void)
+int fsl_initdram(void)
{
phys_size_t dram_size;
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- return initdram();
+ return fsl_initdram();
}
#ifdef CONFIG_FSL_ESDHC
#endif
}
-int initdram(void)
+int fsl_initdram(void)
{
phys_size_t dram_size;
#include <common.h>
#include <i2c.h>
#include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- initdram();
+ fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
}
#endif
-int initdram(void)
+int fsl_initdram(void)
{
phys_size_t dram_size;
popts->cpo_sample = 0x70;
}
-int initdram(void)
+int fsl_initdram(void)
{
phys_size_t dram_size;
#include <common.h>
#include <i2c.h>
#include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- initdram();
+ fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
popts->cpo_sample = 0x70;
}
-int initdram(void)
+int fsl_initdram(void)
{
phys_size_t dram_size;
return 0;
}
#endif
-int initdram(void)
+
+int fsl_initdram(void)
{
puts("Initializing DDR....");
}
}
-int initdram(void)
+int fsl_initdram(void)
{
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
}
}
-int initdram(void)
+int fsl_initdram(void)
{
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
int max_freq;
fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
+
+/**
+ * fsl_initdram() - Set up the SDRAM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsl_initdram(void);
+
#endif