+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -S %s | FileCheck %s
; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
ret i64 %res
}
+define i64 @test_vectorize_select_umin_idx_all_exit_inst(ptr %src, ptr %umin) {
+; CHECK-LABEL: @test_vectorize_select_umin_idx_all_exit_inst(
+; CHECK-NOT: vector.body:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
+ %min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
+ %gep = getelementptr i64, ptr %src, i64 %iv
+ %l = load i64, ptr %gep
+ %cmp = icmp ugt i64 %min.val, %l
+ %min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)
+ %min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
+ %iv.next = add nuw nsw i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 0
+ br i1 %exitcond.not, label %exit, label %loop
+
+exit:
+ %res = phi i64 [ %min.idx.next, %loop ]
+ %res.umin = phi i64 [ %min.val.next, %loop ]
+ store i64 %res.umin, ptr %umin
+ ret i64 %res
+}
+
define i64 @test_vectorize_select_umin_idx_min_ops_switched(ptr %src) {
; CHECK-LABEL: @test_vectorize_select_umin_idx_min_ops_switched(
; CHECK-NOT: vector.body: