+2011-10-20 Kirill Yukhin <kirill.yukhin@intel.com>
+
+ PR target/50766
+ * config/i386/i386.md (bmi_bextr_<mode>): Update register/
+ memory operand order.
+ (bmi2_bzhi_<mode>3): Ditto.
+ (bmi2_pdep_<mode>3): Ditto.
+ (bmi2_pext_<mode>3): Ditto.
+
2011-10-20 Richard Henderson <rth@redhat.com>
* target.def (vec_perm_const_ok): Rename from builtin_vec_perm_ok.
(define_insn "bmi_bextr_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_BEXTR))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI"
;; BMI2 instructions.
(define_insn "bmi2_bzhi_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (and:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (and:SWI48 (match_operand:SWI48 1 "register_operand" "r")
(lshiftrt:SWI48 (const_int -1)
- (match_operand:SWI48 2 "register_operand" "r"))))
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2"
"bzhi\t{%2, %1, %0|%0, %1, %2}"
(define_insn "bmi2_pdep_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PDEP))]
"TARGET_BMI2"
"pdep\t{%2, %1, %0|%0, %1, %2}"
(define_insn "bmi2_pext_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
- (match_operand:SWI48 2 "register_operand" "r")]
+ (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
+ (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
UNSPEC_PEXT))]
"TARGET_BMI2"
"pext\t{%2, %1, %0|%0, %1, %2}"