drm/amdgpu: add interface for setting MGCG perfmon

Enable Navi1X MGCG perfmon setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 258498cbf1ebaaff027b8e49ce74e255d09edfc0..190753930b1190d338106d6840824902f71c0c4f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -218,6 +218,7 @@ struct amdgpu_gfx_funcs {
        void (*reset_ras_error_count) (struct amdgpu_device *adev);
        void (*init_spm_golden)(struct amdgpu_device *adev);
        void (*query_ras_error_status) (struct amdgpu_device *adev);
+       void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
 };
 
 struct sq_work {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8fc69c208adb8bc7c7bba65b47ac351e9e4dcccc..931263331fc7b8d52e4fc1414c79da311289ad2d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4279,6 +4279,21 @@ static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
        nv_grbm_select(adev, me, pipe, q, vm);
  }
 
+static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
+                                         bool enable)
+{
+       uint32_t data, def;
+
+       data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
+
+       if (enable)
+               data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+       else
+               data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+
+       if (data != def)
+               WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
+}
 
 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
        .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
@@ -4288,6 +4303,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
        .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
        .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
        .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
+       .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
 };
 
 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)