global: Migrate CONFIG_SMP_PEN_ADDR to CFG
authorTom Rini <trini@konsulko.com>
Sun, 4 Dec 2022 15:13:54 +0000 (10:13 -0500)
committerTom Rini <trini@konsulko.com>
Fri, 23 Dec 2022 15:15:12 +0000 (10:15 -0500)
Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
arch/arm/cpu/armv7/nonsec_virt.S
board/samsung/arndale/arndale.c
include/configs/arndale.h
include/configs/km/pg-wcom-ls102xa.h
include/configs/ls1021aiot.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h

index a303039..9004074 100644 (file)
@@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
        bx      lr
 ENDPROC(_nonsec_init)
 
-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
 WEAK(smp_waitloop)
        wfi
-       ldr     r1, =CONFIG_SMP_PEN_ADDR        @ load start address
+       ldr     r1, =CFG_SMP_PEN_ADDR   @ load start address
        ldr     r1, [r1]
 #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
        rev     r1, r1
index a992dc6..3ebf600 100644 (file)
@@ -112,10 +112,10 @@ int checkboard(void)
 }
 #endif
 
-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
-       writel(addr, CONFIG_SMP_PEN_ADDR);
+       writel(addr, CFG_SMP_PEN_ADDR);
 
        /* make sure this write is really executed */
        __asm__ volatile ("dsb\n");
index 8acc525..b56effc 100644 (file)
@@ -16,7 +16,7 @@
 
 /* Miscellaneous configurable options */
 
-#define CONFIG_SMP_PEN_ADDR    0x02020000
+#define CFG_SMP_PEN_ADDR       0x02020000
 
 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
 #define CFG_ARM_GIC_BASE_ADDRESS       0x10480000
index 423bb77..15ef68a 100644 (file)
                                        {1, {I2C_NULL_HOP}                 }, \
                                }
 
-#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CFG_SMP_PEN_ADDR               0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256
 
index 53d9936..83ab94e 100644 (file)
@@ -68,7 +68,7 @@
 
 #define FSL_PCIE_COMPAT                "fsl,ls1021a-pcie"
 
-#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CFG_SMP_PEN_ADDR               0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256
 
index 78432e5..e4e5522 100644 (file)
  * MMC
  */
 
-#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CFG_SMP_PEN_ADDR               0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256
 
index a387eea..eb8fb04 100644 (file)
 
 /* GPIO */
 
-#define CONFIG_SMP_PEN_ADDR            0x01ee0200
+#define CFG_SMP_PEN_ADDR               0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256