net: gem: Do not setup any clock for Xilinx SoC Versal
authorMichal Simek <michal.simek@xilinx.com>
Wed, 22 Aug 2018 14:18:34 +0000 (16:18 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 16 Oct 2018 14:53:24 +0000 (16:53 +0200)
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/net/zynq_gem.c

index e22d048..bc33126 100644 (file)
@@ -461,6 +461,7 @@ static int zynq_gem_init(struct udevice *dev)
                break;
        }
 
+#if !defined(CONFIG_ARCH_VERSAL)
        ret = clk_set_rate(&priv->clk, clk_rate);
        if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
                dev_err(dev, "failed to set tx clock rate\n");
@@ -472,6 +473,9 @@ static int zynq_gem_init(struct udevice *dev)
                dev_err(dev, "failed to enable tx clock\n");
                return ret;
        }
+#else
+       debug("requested clk_rate %ld\n", clk_rate);
+#endif
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
                                        ZYNQ_GEM_NWCTRL_TXEN_MASK);