drm/i915/gt: Reapply ppgtt enabling after engine resets

The GFX_MODE is reset along with the engine, turning off ppGTT. We need
to re-enable it upon resume afterwards.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210114101451.24762-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 680bd94..0f02afe 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -27,8 +27,6 @@ void gen7_ppgtt_enable(struct intel_gt *gt)
 {
        struct drm_i915_private *i915 = gt->i915;
        struct intel_uncore *uncore = gt->uncore;
-       struct intel_engine_cs *engine;
-       enum intel_engine_id id;
        u32 ecochk;
 
        intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
@@ -41,13 +39,6 @@ void gen7_ppgtt_enable(struct intel_gt *gt)
                ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
        }
        intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
-
-       for_each_engine(engine, gt, id) {
-               /* GFX_MODE is per-ring on gen7+ */
-               ENGINE_WRITE(engine,
-                            RING_MODE_GEN7,
-                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-       }
 }
 
 void gen6_ppgtt_enable(struct intel_gt *gt)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 20f4272..01553f0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -189,9 +189,16 @@ static void set_pp_dir(struct intel_engine_cs *engine)
 {
        struct i915_address_space *vm = vm_alias(engine->gt->vm);
 
-       if (vm) {
-               ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
-               ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
+       if (!vm)
+               return;
+
+       ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
+       ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
+
+       if (INTEL_GEN(engine->i915) >= 7) {
+               ENGINE_WRITE(engine,
+                            RING_MODE_GEN7,
+                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
        }
 }