[X86] combineAdd - fold ADD(ADC(Y,0,W),X) -> ADC(X,Y,W)

This also exposed a missed ADC canonicalization of constant ops to the RHS

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1670da8..fe9cbdb 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -52262,6 +52262,11 @@ static SDValue combineADC(SDNode *N, SelectionDAG &DAG,
   SDValue RHS = N->getOperand(1);
   SDValue CarryIn = N->getOperand(2);
 
+  // Canonicalize constant to RHS.
+  if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS))
+    return DAG.getNode(X86ISD::ADC, SDLoc(N), N->getVTList(), RHS, LHS,
+                       CarryIn);
+
   // If the LHS and RHS of the ADC node are zero, then it can't overflow and
   // the result is either zero or one (depending on the input carry bit).
   // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
@@ -52904,6 +52909,14 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
     }
   }
 
+  // Fold ADD(ADC(Y,0,W),X) -> ADC(X,Y,W)
+  if (Op0.getOpcode() == X86ISD::ADC && Op0->hasOneUse() &&
+      X86::isZeroNode(Op0.getOperand(1))) {
+    assert(!Op0->hasAnyUseOfValue(1) && "Overflow bit in use");
+    return DAG.getNode(X86ISD::ADC, SDLoc(Op0), Op0->getVTList(), Op1,
+                       Op0.getOperand(0), Op0.getOperand(2));
+  }
+
   return combineAddOrSubToADCOrSBB(N, DAG);
 }
 

diff --git a/llvm/test/CodeGen/X86/combine-add.ll b/llvm/test/CodeGen/X86/combine-add.ll
index 510a1ac..3d7fb11 100644 (file)
--- a/llvm/test/CodeGen/X86/combine-add.ll
+++ b/llvm/test/CodeGen/X86/combine-add.ll
@@ -376,14 +376,12 @@ define <4 x i32> @combine_vec_add_add_not(<4 x i32> %a, <4 x i32> %b) {
   ret <4 x i32> %r
 }
 
-; FIXME: Fold to adc $32, %edi
 define i32 @combine_add_adc_constant(i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: combine_add_adc_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    btl $7, %edx
-; CHECK-NEXT:    adcl $0, %edi
-; CHECK-NEXT:    leal 32(%rdi), %eax
+; CHECK-NEXT:    adcl $32, %eax
 ; CHECK-NEXT:    retq
   %and = lshr i32 %z, 7
   %bit = and i32 %and, 1