anv no longer supports versions below this.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
if (total_push_constants_size == 0)
return (struct anv_state) { .offset = 0 };
- const unsigned push_constant_alignment =
- cmd_buffer->device->info->ver < 8 ? 32 : 64;
+ const unsigned push_constant_alignment = 64;
const unsigned aligned_total_push_constants_size =
ALIGN(total_push_constants_size, push_constant_alignment);
struct anv_state state;
env_var_as_boolean("ANV_EXPERIMENTAL_NV_MESH_SHADER", false);
*ext = (struct vk_device_extension_table) {
- .KHR_8bit_storage = device->info.ver >= 8,
- .KHR_16bit_storage = device->info.ver >= 8,
+ .KHR_8bit_storage = true,
+ .KHR_16bit_storage = true,
.KHR_bind_memory2 = true,
.KHR_buffer_device_address = device->has_a64_buffer_access,
.KHR_copy_commands2 = true,
.KHR_sampler_mirror_clamp_to_edge = true,
.KHR_sampler_ycbcr_conversion = true,
.KHR_separate_depth_stencil_layouts = true,
- .KHR_shader_atomic_int64 = device->info.ver >= 9,
+ .KHR_shader_atomic_int64 = true,
.KHR_shader_clock = true,
.KHR_shader_draw_parameters = true,
- .KHR_shader_float16_int8 = device->info.ver >= 8,
- .KHR_shader_float_controls = device->info.ver >= 8,
+ .KHR_shader_float16_int8 = true,
+ .KHR_shader_float_controls = true,
.KHR_shader_integer_dot_product = true,
.KHR_shader_non_semantic_info = true,
- .KHR_shader_subgroup_extended_types = device->info.ver >= 8,
+ .KHR_shader_subgroup_extended_types = true,
.KHR_shader_subgroup_uniform_control_flow = true,
.KHR_shader_terminate_invocation = true,
.KHR_spirv_1_4 = true,
.KHR_workgroup_memory_explicit_layout = true,
.KHR_zero_initialize_workgroup_memory = true,
.EXT_4444_formats = true,
- .EXT_border_color_swizzle = device->info.ver >= 8,
+ .EXT_border_color_swizzle = true,
.EXT_buffer_device_address = device->has_a64_buffer_access,
.EXT_calibrated_timestamps = device->has_reg_timestamp,
.EXT_color_write_enable = true,
.EXT_conditional_rendering = true,
- .EXT_conservative_rasterization = device->info.ver >= 9,
- .EXT_custom_border_color = device->info.ver >= 8,
+ .EXT_conservative_rasterization = true,
+ .EXT_custom_border_color = true,
.EXT_depth_clip_control = true,
.EXT_depth_clip_enable = true,
.EXT_descriptor_indexing = device->has_a64_buffer_access &&
.EXT_extended_dynamic_state2 = true,
.EXT_external_memory_dma_buf = true,
.EXT_external_memory_host = true,
- .EXT_fragment_shader_interlock = device->info.ver >= 9,
+ .EXT_fragment_shader_interlock = true,
.EXT_global_priority = device->max_context_priority >=
INTEL_CONTEXT_MEDIUM_PRIORITY,
.EXT_global_priority_query = device->max_context_priority >=
.EXT_physical_device_drm = true,
.EXT_pipeline_creation_cache_control = true,
.EXT_pipeline_creation_feedback = true,
- .EXT_post_depth_coverage = device->info.ver >= 9,
+ .EXT_post_depth_coverage = true,
.EXT_primitives_generated_query = true,
.EXT_primitive_topology_list_restart = true,
.EXT_private_data = true,
.EXT_queue_family_foreign = true,
.EXT_robustness2 = true,
.EXT_sample_locations = true,
- .EXT_sampler_filter_minmax = device->info.ver >= 9,
+ .EXT_sampler_filter_minmax = true,
.EXT_scalar_block_layout = true,
.EXT_separate_stencil_usage = true,
.EXT_shader_atomic_float = true,
- .EXT_shader_atomic_float2 = device->info.ver >= 9,
+ .EXT_shader_atomic_float2 = true,
.EXT_shader_demote_to_helper_invocation = true,
.EXT_shader_module_identifier = true,
- .EXT_shader_stencil_export = device->info.ver >= 9,
+ .EXT_shader_stencil_export = true,
.EXT_shader_subgroup_ballot = true,
.EXT_shader_subgroup_vote = true,
.EXT_shader_viewport_index_layer = true,
.GOOGLE_user_type = true,
.INTEL_performance_query = device->perf &&
device->perf->i915_perf_version >= 3,
- .INTEL_shader_integer_functions2 = device->info.ver >= 8,
+ .INTEL_shader_integer_functions2 = true,
.EXT_multi_draw = true,
.NV_compute_shader_derivatives = true,
.NV_mesh_shader = device->info.has_mesh_shading &&
goto fail_base;
}
- device->use_relocations = device->info.ver < 8 ||
- device->info.platform == INTEL_PLATFORM_CHV;
+ device->use_relocations = false;
if (!device->use_relocations &&
!anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN)) {
/* We only allow 48-bit addresses with softpin because knowing the actual
* address is required for the vertex cache flush workaround.
*/
- device->supports_48bit_addresses = (device->info.ver >= 8) &&
- device->gtt_size > (4ULL << 30 /* GiB */);
+ device->supports_48bit_addresses =
+ device->gtt_size > (4ULL << 30 /* GiB */);
result = anv_physical_device_init_heaps(device, fd);
if (result != VK_SUCCESS)
/* We first got the A64 messages on broadwell and we can only use them if
* we can pass addresses directly into the shader which requires softpin.
*/
- device->has_a64_buffer_access = device->info.ver >= 8 &&
- device->use_softpin;
+ device->has_a64_buffer_access = device->use_softpin;
- /* We first get bindless image access on Skylake.
- */
- device->has_bindless_images = device->info.ver >= 9;
-
- /* We've had bindless samplers since Ivy Bridge (forever in Vulkan terms)
- * because it's just a matter of setting the sampler address in the sample
- * message header. However, we've not bothered to wire it up for vec4 so
- * we leave it disabled on gfx7.
- */
- device->has_bindless_samplers = device->info.ver >= 8;
+ device->has_bindless_images = true;
+ device->has_bindless_samplers = true;
device->has_implicit_ccs = device->info.has_aux_map ||
device->info.verx10 >= 125;
device->compiler->shader_debug_log = compiler_debug_log;
device->compiler->shader_perf_log = compiler_perf_log;
device->compiler->constant_buffer_0_is_relative =
- device->info.ver < 8 || !device->has_context_isolation;
+ !device->has_context_isolation;
device->compiler->supports_shader_constants = true;
device->compiler->indirect_ubos_use_sampler = device->info.ver < 12;
.alphaToOne = true,
.multiViewport = true,
.samplerAnisotropy = true,
- .textureCompressionETC2 = pdevice->info.ver >= 8 ||
- pdevice->info.platform == INTEL_PLATFORM_BYT,
+ .textureCompressionETC2 = true,
.textureCompressionASTC_LDR = has_astc_ldr,
.textureCompressionBC = true,
.occlusionQueryPrecise = true,
.shaderStorageImageArrayDynamicIndexing = true,
.shaderClipDistance = true,
.shaderCullDistance = true,
- .shaderFloat64 = pdevice->info.ver >= 8 &&
- pdevice->info.has_64bit_float,
- .shaderInt64 = pdevice->info.ver >= 8,
- .shaderInt16 = pdevice->info.ver >= 8,
- .shaderResourceMinLod = pdevice->info.ver >= 9,
+ .shaderFloat64 = pdevice->info.has_64bit_float,
+ .shaderInt64 = true,
+ .shaderInt16 = true,
+ .shaderResourceMinLod = true,
.variableMultisampleRate = true,
.inheritedQueries = true,
};
{
assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
- f->storageBuffer16BitAccess = pdevice->info.ver >= 8;
- f->uniformAndStorageBuffer16BitAccess = pdevice->info.ver >= 8;
- f->storagePushConstant16 = pdevice->info.ver >= 8;
+ f->storageBuffer16BitAccess = true;
+ f->uniformAndStorageBuffer16BitAccess = true;
+ f->storagePushConstant16 = true;
f->storageInputOutput16 = false;
f->multiview = true;
f->multiviewGeometryShader = true;
f->samplerMirrorClampToEdge = true;
f->drawIndirectCount = true;
- f->storageBuffer8BitAccess = pdevice->info.ver >= 8;
- f->uniformAndStorageBuffer8BitAccess = pdevice->info.ver >= 8;
- f->storagePushConstant8 = pdevice->info.ver >= 8;
- f->shaderBufferInt64Atomics = pdevice->info.ver >= 9;
+ f->storageBuffer8BitAccess = true;
+ f->uniformAndStorageBuffer8BitAccess = true;
+ f->storagePushConstant8 = true;
+ f->shaderBufferInt64Atomics = true;
f->shaderSharedInt64Atomics = false;
- f->shaderFloat16 = pdevice->info.ver >= 8;
- f->shaderInt8 = pdevice->info.ver >= 8;
+ f->shaderFloat16 = true;
+ f->shaderInt8 = true;
bool descIndexing = pdevice->has_a64_buffer_access &&
pdevice->has_bindless_images;
f->descriptorBindingVariableDescriptorCount = descIndexing;
f->runtimeDescriptorArray = descIndexing;
- f->samplerFilterMinmax = pdevice->info.ver >= 9;
+ f->samplerFilterMinmax = true;
f->scalarBlockLayout = true;
f->imagelessFramebuffer = true;
f->uniformBufferStandardLayout = true;
VkPhysicalDeviceImage2DViewOf3DFeaturesEXT *features =
(VkPhysicalDeviceImage2DViewOf3DFeaturesEXT *)ext;
features->image2DViewOf3D = true;
- features->sampler2DViewOf3D = pdevice->info.ver >= 9;
+ features->sampler2DViewOf3D = true;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
(VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
- features->customBorderColors = pdevice->info.ver >= 8;
- features->customBorderColorWithoutFormat = pdevice->info.ver >= 8;
+ features->customBorderColors = true;
+ features->customBorderColorWithoutFormat = true;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FRAGMENT_SHADER_INTERLOCK_FEATURES_EXT: {
VkPhysicalDeviceFragmentShaderInterlockFeaturesEXT *features =
(VkPhysicalDeviceFragmentShaderInterlockFeaturesEXT *)ext;
- features->fragmentShaderSampleInterlock = pdevice->info.ver >= 9;
- features->fragmentShaderPixelInterlock = pdevice->info.ver >= 9;
+ features->fragmentShaderSampleInterlock = true;
+ features->fragmentShaderPixelInterlock = true;
features->fragmentShaderShadingRateInterlock = false;
break;
}
features->shaderBufferFloat16Atomics = false;
features->shaderBufferFloat16AtomicAdd = false;
features->shaderBufferFloat16AtomicMinMax = false;
- features->shaderBufferFloat32AtomicMinMax = pdevice->info.ver >= 9;
+ features->shaderBufferFloat32AtomicMinMax = true;
features->shaderBufferFloat64AtomicMinMax =
pdevice->info.has_64bit_float && pdevice->info.has_lsc;
features->shaderSharedFloat16Atomics = false;
features->shaderSharedFloat16AtomicAdd = false;
features->shaderSharedFloat16AtomicMinMax = false;
- features->shaderSharedFloat32AtomicMinMax = pdevice->info.ver >= 9;
+ features->shaderSharedFloat32AtomicMinMax = true;
features->shaderSharedFloat64AtomicMinMax = false;
features->shaderImageFloat32AtomicMinMax = false;
features->sparseImageFloat32AtomicMinMax = false;
* VERTEX_ELEMENT_STATE::Source Element Offset: [0,2047]
*/
.maxVertexInputAttributeOffset = 2047,
- /* Broadwell PRMs: Volume 2d: Command Reference: Structures:
- *
- * VERTEX_BUFFER_STATE::Buffer Pitch: [0,2048]
- *
- * Skylake PRMs: Volume 2d: Command Reference: Structures:
+ /* Skylake PRMs: Volume 2d: Command Reference: Structures:
*
* VERTEX_BUFFER_STATE::Buffer Pitch: [0,4095]
*/
- .maxVertexInputBindingStride = devinfo->ver < 9 ? 2048 : 4095,
+ .maxVertexInputBindingStride = 4095,
.maxVertexOutputComponents = 128,
.maxTessellationGenerationLevel = 64,
.maxTessellationPatchSize = 32,
.maxTessellationEvaluationInputComponents = 128,
.maxTessellationEvaluationOutputComponents = 128,
.maxGeometryShaderInvocations = 32,
- .maxGeometryInputComponents = devinfo->ver >= 8 ? 128 : 64,
+ .maxGeometryInputComponents = 128,
.maxGeometryOutputComponents = 128,
.maxGeometryOutputVertices = 256,
.maxGeometryTotalOutputComponents = 1024,
* Since the Windows driver does the same, it's probably fair to assume
* that no one needs more than this.
*/
- .lineWidthRange = { 0.0, devinfo->ver >= 9 ? 8.0 : 7.9921875 },
+ .lineWidthRange = { 0.0, 8.0 },
.pointSizeGranularity = (1.0 / 8.0),
.lineWidthGranularity = (1.0 / 128.0),
.strictLines = false,
VK_SUBGROUP_FEATURE_BALLOT_BIT |
VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
- VK_SUBGROUP_FEATURE_QUAD_BIT;
- if (pdevice->info.ver >= 8) {
- /* TODO: There's no technical reason why these can't be made to
- * work on gfx7 but they don't at the moment so it's best to leave
- * the feature disabled than enabled and broken.
- */
- p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
- VK_SUBGROUP_FEATURE_CLUSTERED_BIT;
- }
- p->subgroupQuadOperationsInAllStages = pdevice->info.ver >= 8;
+ VK_SUBGROUP_FEATURE_QUAD_BIT |
+ VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
+ VK_SUBGROUP_FEATURE_CLUSTERED_BIT;
+ p->subgroupQuadOperationsInAllStages = true;
p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_USER_CLIP_PLANES_ONLY;
p->maxMultiviewViewCount = 16;
VK_RESOLVE_MODE_MIN_BIT |
VK_RESOLVE_MODE_MAX_BIT;
/* Average doesn't make sense for stencil so we don't support that */
- p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT;
- if (pdevice->info.ver >= 8) {
- /* The advanced stencil resolve modes currently require stencil
- * sampling be supported by the hardware.
- */
- p->supportedStencilResolveModes |= VK_RESOLVE_MODE_MIN_BIT |
- VK_RESOLVE_MODE_MAX_BIT;
- }
+ p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT |
+ VK_RESOLVE_MODE_MIN_BIT |
+ VK_RESOLVE_MODE_MAX_BIT;
p->independentResolveNone = true;
p->independentResolve = true;
- p->filterMinmaxSingleComponentFormats = pdevice->info.ver >= 9;
- p->filterMinmaxImageComponentMapping = pdevice->info.ver >= 9;
+ p->filterMinmaxSingleComponentFormats = true;
+ p->filterMinmaxImageComponentMapping = true;
p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
* command parser gets in the way and we have to fall back to growing
* the batch.
*/
- device->can_chain_batches = device->info->ver >= 8;
+ device->can_chain_batches = true;
device->robust_buffer_access = robust_buffer_access;
if (result != VK_SUCCESS)
goto fail_general_state_pool;
- if (device->info->ver >= 8) {
- /* The border color pointer is limited to 24 bits, so we need to make
- * sure that any such color used at any point in the program doesn't
- * exceed that limit.
- * We achieve that by reserving all the custom border colors we support
- * right off the bat, so they are close to the base address.
- */
- anv_state_reserved_pool_init(&device->custom_border_colors,
- &device->dynamic_state_pool,
- MAX_CUSTOM_BORDER_COLORS,
- sizeof(struct gfx8_border_color), 64);
- }
+ /* The border color pointer is limited to 24 bits, so we need to make
+ * sure that any such color used at any point in the program doesn't
+ * exceed that limit.
+ * We achieve that by reserving all the custom border colors we support
+ * right off the bat, so they are close to the base address.
+ */
+ anv_state_reserved_pool_init(&device->custom_border_colors,
+ &device->dynamic_state_pool,
+ MAX_CUSTOM_BORDER_COLORS,
+ sizeof(struct gfx8_border_color), 64);
result = anv_state_pool_init(&device->instruction_state_pool, device,
"instruction pool",
fail_instruction_state_pool:
anv_state_pool_finish(&device->instruction_state_pool);
fail_dynamic_state_pool:
- if (device->info->ver >= 8)
- anv_state_reserved_pool_finish(&device->custom_border_colors);
+ anv_state_reserved_pool_finish(&device->custom_border_colors);
anv_state_pool_finish(&device->dynamic_state_pool);
fail_general_state_pool:
anv_state_pool_finish(&device->general_state_pool);
/* We only need to free these to prevent valgrind errors. The backing
* BO will go away in a couple of lines so we don't actually leak.
*/
- if (device->info->ver >= 8)
- anv_state_reserved_pool_finish(&device->custom_border_colors);
+ anv_state_reserved_pool_finish(&device->custom_border_colors);
anv_state_pool_free(&device->dynamic_state_pool, device->border_colors);
anv_state_pool_free(&device->dynamic_state_pool, device->slice_hash);
anv_state_pool_free(&device->dynamic_state_pool, device->cps_states);
}
}
- /* The B4G4R4A4 format isn't available prior to Broadwell so we have to fall
- * back to a format with a more complex swizzle.
- */
- if (vk_format == VK_FORMAT_B4G4R4A4_UNORM_PACK16 && devinfo->ver < 8) {
- plane_format.isl_format = ISL_FORMAT_B4G4R4A4_UNORM;
- plane_format.swizzle = ISL_SWIZZLE(GREEN, RED, ALPHA, BLUE);
- }
-
return plane_format;
}
VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT |
VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT;
- if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
- flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
-
- if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->ver >= 9)
- flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT;
-
- if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
- flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_DEPTH_COMPARISON_BIT;
+ if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
+ flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT |
+ VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT |
+ VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_DEPTH_COMPARISON_BIT;
+ }
return flags;
}
return VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT |
VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT;
- flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT;
-
- if (devinfo->ver >= 9)
- flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT;
+ flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT |
+ VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT;
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
flags |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
maxExtent.width = 2048;
maxExtent.height = 2048;
maxExtent.depth = 2048;
- /* Prior to SKL, the mipmaps for 3D surfaces are laid out in a way
- * that make it impossible to represent in the way that
- * VkSubresourceLayout expects. Since we can't tell users how to make
- * sense of them, don't report them as available.
- */
- if (devinfo->ver < 9 && info->tiling == VK_IMAGE_TILING_LINEAR)
- maxMipLevels = 1;
- else
- maxMipLevels = 12; /* log2(maxWidth) + 1 */
+ maxMipLevels = 12; /* log2(maxWidth) + 1 */
maxArraySize = 1;
sampleCounts = VK_SAMPLE_COUNT_1_BIT;
break;
}
/* From the bspec section entitled "Surface Layout and Tiling",
- * pre-gfx9 has a 2 GB limitation of the size in bytes,
- * gfx9 and gfx10 have a 256 GB limitation and gfx11+
- * has a 16 TB limitation.
+ * Gfx9 has a 256 GB limitation and Gfx11+ has a 16 TB limitation.
*/
uint64_t maxResourceSize = 0;
- if (devinfo->ver < 9)
- maxResourceSize = (uint64_t) 1 << 31;
- else if (devinfo->ver < 11)
+ if (devinfo->ver < 11)
maxResourceSize = (uint64_t) 1 << 38;
else
maxResourceSize = (uint64_t) 1 << 44;
void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer);
-void genX(cmd_buffer_emit_gfx7_depth_flush)(struct anv_cmd_buffer *cmd_buffer);
-
void genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
const struct isl_surf *surf);
* value (SKL+), define the clear value to the optimal constant.
*/
union isl_color_value default_clear_color = { .u32 = { 0, } };
- if (device->info->ver >= 9 && aspect == VK_IMAGE_ASPECT_DEPTH_BIT)
+ if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT)
default_clear_color.f32[0] = ANV_HZ_FC_VAL;
if (!clear_color)
clear_color = &default_clear_color;
general_aux_usage, NULL,
ANV_IMAGE_VIEW_STATE_STORAGE_LOWERED,
&iview->planes[vplane].lowered_storage_surface_state,
- device->info->ver >= 9 ? NULL :
- &iview->planes[vplane].lowered_storage_image_param);
+ NULL);
} else {
/* In this case, we support the format but, because there's no
* SPIR-V format specifier corresponding to it, we only support it
void
anv_physical_device_init_perf(struct anv_physical_device *device, int fd)
{
- const struct intel_device_info *devinfo = &device->info;
-
device->perf = NULL;
- /* We need self modifying batches. The i915 parser prevents it on
- * Gfx7.5 :( maybe one day.
- */
- if (devinfo->ver < 8)
- return;
-
struct intel_perf_config *perf = intel_perf_new(NULL);
intel_perf_init_metrics(perf, &device->info, fd,
properties[p++] = metric_id;
properties[p++] = DRM_I915_PERF_PROP_OA_FORMAT;
- properties[p++] = device->info->ver >= 8 ?
- I915_OA_FORMAT_A32u40_A4u32_B8_C8 :
- I915_OA_FORMAT_A45_B8_C8;
+ properties[p++] = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
properties[p++] = DRM_I915_PERF_PROP_OA_EXPONENT;
properties[p++] = 31; /* slowest sampling period */
.descriptor_indexing = true,
.device_group = true,
.draw_parameters = true,
- .float16 = pdevice->info.ver >= 8,
+ .float16 = true,
.float32_atomic_add = pdevice->info.has_lsc,
- .float32_atomic_min_max = pdevice->info.ver >= 9,
- .float64 = pdevice->info.ver >= 8,
+ .float32_atomic_min_max = true,
+ .float64 = true,
.float64_atomic_min_max = pdevice->info.has_lsc,
- .fragment_shader_sample_interlock = pdevice->info.ver >= 9,
- .fragment_shader_pixel_interlock = pdevice->info.ver >= 9,
+ .fragment_shader_sample_interlock = true,
+ .fragment_shader_pixel_interlock = true,
.geometry_streams = true,
/* When using Vulkan 1.3 or KHR_format_feature_flags2 is enabled, the
* read/write without format is per format, so just report true. It's
*/
.image_read_without_format = instance->vk.app_info.api_version >= VK_API_VERSION_1_3 || device->vk.enabled_extensions.KHR_format_feature_flags2,
.image_write_without_format = true,
- .int8 = pdevice->info.ver >= 8,
- .int16 = pdevice->info.ver >= 8,
- .int64 = pdevice->info.ver >= 8,
- .int64_atomics = pdevice->info.ver >= 9 && pdevice->use_softpin,
- .integer_functions2 = pdevice->info.ver >= 8,
+ .int8 = true,
+ .int16 = true,
+ .int64 = true,
+ .int64_atomics = pdevice->use_softpin,
+ .integer_functions2 = true,
.mesh_shading_nv = pdevice->vk.supported_extensions.NV_mesh_shader,
.min_lod = true,
.multiview = true,
.physical_storage_buffer_address = pdevice->has_a64_buffer_access,
- .post_depth_coverage = pdevice->info.ver >= 9,
+ .post_depth_coverage = true,
.runtime_descriptor_array = true,
- .float_controls = pdevice->info.ver >= 8,
+ .float_controls = true,
.ray_query = pdevice->info.has_ray_tracing,
.ray_tracing = pdevice->info.has_ray_tracing,
.shader_clock = true,
.shader_viewport_index_layer = true,
- .stencil_export = pdevice->info.ver >= 9,
- .storage_8bit = pdevice->info.ver >= 8,
- .storage_16bit = pdevice->info.ver >= 8,
+ .stencil_export = true,
+ .storage_8bit = true,
+ .storage_16bit = true,
.subgroup_arithmetic = true,
.subgroup_basic = true,
.subgroup_ballot = true,
.subgroup_shuffle = true,
.subgroup_vote = true,
.tessellation = true,
- .transform_feedback = pdevice->info.ver >= 8,
+ .transform_feedback = true,
.variable_pointers = true,
.vk_memory_model = true,
.vk_memory_model_device_scope = true,
* so we can just use it unconditionally. This may not be quite as
* efficient but it saves us from recompiling.
*/
- if (devinfo->ver >= 9)
- key->msaa_16 = ~0;
+ key->msaa_16 = ~0;
- /* XXX: Handle texture swizzle on HSW- */
for (int i = 0; i < BRW_MAX_SAMPLERS; i++) {
/* Assume color sampler, no swizzling. (Works for BDW+) */
key->swizzles[i] = SWIZZLE_XYZW;
memset(key, 0, sizeof(*key));
populate_base_prog_key(device, robust_buffer_acccess, &key->base);
-
- /* XXX: Handle vertex input work-arounds */
-
- /* XXX: Handle sampler_prog_key */
}
static void
*/
tcs_stage->key.tcs._tes_primitive_mode =
tes_stage->nir->info.tess._primitive_mode;
- tcs_stage->key.tcs.quads_workaround =
- compiler->devinfo->ver < 9 &&
- tes_stage->nir->info.tess._primitive_mode == TESS_PRIMITIVE_QUADS &&
- tes_stage->nir->info.tess.spacing == TESS_SPACING_EQUAL;
}
static void
static inline void
write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
{
- unsigned reloc_size = 0;
- if (device->info->ver >= 8) {
- reloc_size = sizeof(uint64_t);
- *(uint64_t *)p = intel_canonical_address(v);
- } else {
- reloc_size = sizeof(uint32_t);
- *(uint32_t *)p = v;
- }
+ unsigned reloc_size = sizeof(uint64_t);
+ *(uint64_t *)p = intel_canonical_address(v);
if (flush && device->physical->memory.need_clflush)
intel_flush_range(p, reloc_size);
}
}
-#if GFX_VER >= 8 && GFX_VER < 10
+#if GFX_VER == 9
static struct blorp_address
blorp_get_surface_base_address(struct blorp_batch *batch)
{
/* Apply any outstanding flushes in case pipeline select haven't. */
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
- genX(cmd_buffer_emit_gfx7_depth_flush)(cmd_buffer);
-
/* BLORP doesn't do anything fancy with depth such as discards, so we want
* the PMA fix off. Also, off is always the safe option.
*/
sba.InstructionMOCS = mocs;
sba.InstructionBaseAddressModifyEnable = true;
-# if (GFX_VER >= 8)
/* Broadwell requires that we specify a buffer size for a bunch of
* these fields. However, since we will be growing the BO's live, we
* just set them all to the maximum.
sba.IndirectObjectBufferSizeModifyEnable = true;
sba.DynamicStateBufferSizeModifyEnable = true;
sba.InstructionBuffersizeModifyEnable = true;
-# else
- /* On gfx7, we have upper bounds instead. According to the docs,
- * setting an upper bound of zero means that no bounds checking is
- * performed so, in theory, we should be able to leave them zero.
- * However, border color is broken and the GPU bounds-checks anyway.
- * To avoid this and other potential problems, we may as well set it
- * for everything.
- */
- sba.GeneralStateAccessUpperBound =
- (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
- sba.GeneralStateAccessUpperBoundModifyEnable = true;
- sba.DynamicStateAccessUpperBound =
- (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
- sba.DynamicStateAccessUpperBoundModifyEnable = true;
- sba.InstructionAccessUpperBound =
- (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
- sba.InstructionAccessUpperBoundModifyEnable = true;
-# endif
-# if (GFX_VER >= 9)
sba.BindlessSurfaceStateBaseAddress =
(struct anv_address) { device->surface_state_pool.block_pool.bo, 0 };
sba.BindlessSurfaceStateSize = (1 << 20) - 1;
sba.BindlessSurfaceStateMOCS = mocs;
sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
-# endif
-# if (GFX_VER >= 10)
+#if GFX_VER >= 11
sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 };
sba.BindlessSamplerStateMOCS = mocs;
sba.BindlessSamplerStateBaseAddressModifyEnable = true;
sba.BindlessSamplerStateBufferSize = 0;
-# endif
+#endif
#if GFX_VERx10 >= 125
sba.L1CacheControl = L1CC_WB;
#endif
render_area.extent.height != iview->vk.extent.height)
return false;
- /* On Broadwell and earlier, we can only handle 0/1 clear colors */
- if (GFX_VER <= 8 &&
- !isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format))
- return false;
-
/* If the clear color is one that would require non-trivial format
* conversion on resolve, we don't bother with the fast clear. This
* shouldn't be common as most clear colors are 0/1 and the most common
struct anv_address addr =
anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
- if (GFX_VER >= 9) {
- const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
- const unsigned num_dwords = GFX_VER >= 10 ?
- isl_dev->ss.clear_color_state_size / 4 :
- isl_dev->ss.clear_value_size / 4;
- for (unsigned i = 0; i < num_dwords; i++) {
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
- sdi.Address = addr;
- sdi.Address.offset += i * 4;
- sdi.ImmediateData = 0;
- }
- }
- } else {
+ const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
+ const unsigned num_dwords = GFX_VER >= 10 ?
+ isl_dev->ss.clear_color_state_size / 4 :
+ isl_dev->ss.clear_value_size / 4;
+ for (unsigned i = 0; i < num_dwords; i++) {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = addr;
- /* Pre-SKL, the dword containing the clear values also contains
- * other fields, so we need to initialize those fields to match the
- * values that would be in a color attachment.
- */
- sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 |
- ISL_CHANNEL_SELECT_GREEN << 22 |
- ISL_CHANNEL_SELECT_BLUE << 19 |
- ISL_CHANNEL_SELECT_ALPHA << 16;
+ sdi.Address.offset += i * 4;
+ sdi.ImmediateData = 0;
}
}
}
}
}
-#if GFX_VER >= 8
/* Emit the sample pattern at the beginning of the batch because the
* default locations emitted at the device initialization might have been
* changed by a previous command buffer.
cmd_buffer->state.conditional_render_enabled =
conditional_rendering_info && conditional_rendering_info->conditionalRenderingEnable;
}
-#endif
return VK_SUCCESS;
}
/* The secondary isn't counted in our VF cache tracking so we need to
* invalidate the whole thing.
*/
- if (GFX_VER >= 8 && GFX_VER <= 9) {
+ if (GFX_VER == 9) {
anv_add_pending_pipe_bits(primary,
ANV_PIPE_CS_STALL_BIT | ANV_PIPE_VF_CACHE_INVALIDATE_BIT,
"Secondary cmd buffer not tracked in VF cache");
if (trace_flush)
trace_intel_begin_stall(&cmd_buffer->trace);
- if ((GFX_VER >= 8 && GFX_VER <= 9) &&
+ if (GFX_VER == 9 &&
(bits & ANV_PIPE_CS_STALL_BIT) &&
(bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) {
/* If we are doing a VF cache invalidate AND a CS stall (it must be
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
c._3DCommandSubOpcode = push_constant_opcodes[stage];
- /* Set MOCS, except on Gfx8, because the Broadwell PRM says:
- *
- * "Constant Buffer Object Control State must be always
- * programmed to zero."
- *
- * This restriction does not exist on any newer platforms.
+ /* Set MOCS.
*
* We only have one MOCS field for the whole packet, not one per
* buffer. We could go out of our way here to walk over all of
*
* Let's not bother and assume it's all internal.
*/
-#if GFX_VER >= 9
c.MOCS = mocs;
-#elif GFX_VER < 8
- c.ConstantBody.MOCS = mocs;
-#endif
if (anv_pipeline_has_stage(pipeline, stage)) {
const struct anv_pipeline_bind_map *bind_map =
};
}
-#if GFX_VER >= 8 && GFX_VER <= 9
+#if GFX_VER == 9
genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, vb,
state.BufferStartingAddress,
state.BufferSize);
cmd_buffer->state.gfx.primitive_topology = topology;
-#if (GFX_VER >= 8)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
vft.PrimitiveTopologyType = topology;
}
-#endif
}
genX(cmd_buffer_flush_dynamic_state)(cmd_buffer);
#if GFX_VER >= 12
.L3BypassDisable = true,
#endif
-#if (GFX_VER >= 8)
.BufferStartingAddress = addr,
.BufferSize = size
-#else
- .BufferStartingAddress = addr,
- .EndAddress = anv_address_add(addr, size),
-#endif
});
genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer,
if (cmd_buffer->state.current_pipeline == pipeline)
return;
-#if GFX_VER >= 8 && GFX_VER < 10
+#if GFX_VER == 9
/* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
*
* Software must clear the COLOR_CALC_STATE Valid field in
*/
if (pipeline == GPGPU)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
-#endif
-#if GFX_VER == 9
if (pipeline == _3D) {
/* There is a mid-object preemption workaround which requires you to
* re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
-#if GFX_VER >= 9
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
-#endif
ps.PipelineSelection = pipeline;
}
}
void
-genX(cmd_buffer_emit_gfx7_depth_flush)(struct anv_cmd_buffer *cmd_buffer)
-{
- if (GFX_VER >= 8)
- return;
-
- /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
- *
- * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
- * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
- * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
- * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
- * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
- * Depth Flush Bit set, followed by another pipelined depth stall
- * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
- * guarantee that the pipeline from WM onwards is already flushed (e.g.,
- * via a preceding MI_FLUSH)."
- */
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
- pipe.DepthStallEnable = true;
- anv_debug_dump_pc(pipe);
- }
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
- pipe.DepthCacheFlushEnable = true;
-#if GFX_VER >= 12
- pipe.TileCacheFlushEnable = true;
-#endif
- anv_debug_dump_pc(pipe);
- }
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
- pipe.DepthStallEnable = true;
- anv_debug_dump_pc(pipe);
- }
-}
-
-void
genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
const struct isl_surf *surf)
{
struct anv_address vb_address,
uint32_t vb_size)
{
- if (GFX_VER < 8 || GFX_VER > 9 ||
- anv_use_relocations(cmd_buffer->device->physical))
+ if (GFX_VER > 9 || anv_use_relocations(cmd_buffer->device->physical))
return;
struct anv_vb_cache_range *bound, *dirty;
uint32_t access_type,
uint64_t vb_used)
{
- if (GFX_VER < 8 || GFX_VER > 9 ||
- anv_use_relocations(cmd_buffer->device->physical))
+ if (GFX_VER > 9 || anv_use_relocations(cmd_buffer->device->physical))
return;
if (access_type == RANDOM) {
/* FIXME: Width and Height are wrong */
- genX(cmd_buffer_emit_gfx7_depth_flush)(cmd_buffer);
-
uint32_t *dw = anv_batch_emit_dwords(&cmd_buffer->batch,
device->isl_dev.ds.size / 4);
if (dw == NULL)
switch (pOverrideInfo->type) {
case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL: {
-#if GFX_VER >= 9
anv_batch_write_reg(&cmd_buffer->batch, GENX(CS_DEBUG_MODE2), csdm2) {
csdm2._3DRenderingInstructionDisable = pOverrideInfo->enable;
csdm2.MediaInstructionDisable = pOverrideInfo->enable;
csdm2._3DRenderingInstructionDisableMask = true;
csdm2.MediaInstructionDisableMask = true;
}
-#else
- anv_batch_write_reg(&cmd_buffer->batch, GENX(INSTPM), instpm) {
- instpm._3DRenderingInstructionDisable = pOverrideInfo->enable;
- instpm.MediaInstructionDisable = pOverrideInfo->enable;
- instpm._3DRenderingInstructionDisableMask = true;
- instpm.MediaInstructionDisableMask = true;
- }
-#endif
break;
}
sbe.ForceVertexURBEntryReadLength = true;
sbe.ForceVertexURBEntryReadOffset = true;
-#if GFX_VER >= 9
for (unsigned i = 0; i < 32; i++)
sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
-#endif
}
/* Emit URB setup. We tell it that the VS is active because we want it to
genX(emit_l3_config)(batch, device, cfg);
anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) {
-#if GFX_VER >= 9
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
-#endif
ps.PipelineSelection = _3D;
}
struct anv_address dst, struct anv_address src,
uint32_t size)
{
- if (GFX_VER >= 8 && GFX_VER <= 9 &&
- !anv_use_relocations(state->device->physical) &&
+ if (GFX_VER == 9 && !anv_use_relocations(state->device->physical) &&
anv_gfx8_9_vb_cache_range_needs_workaround(&state->vb_bound,
&state->vb_dirty,
src, size)) {
.ConstantInterpolationEnable = wm_prog_data->flat_inputs,
};
-#if GFX_VER >= 9
for (unsigned i = 0; i < 32; i++)
sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
-#endif
/* On Broadwell, they broke 3DSTATE_SBE into two packets */
struct GENX(3DSTATE_SBE_SWIZ) swiz = {
raster.BackFaceFillMode = genX(vk_to_intel_fillmode)[rs->polygon_mode];
raster.ScissorRectangleEnable = true;
-#if GFX_VER >= 9
- /* GFX9+ splits ViewportZClipTestEnable into near and far enable bits */
raster.ViewportZFarClipTestEnable = pipeline->depth_clip_enable;
raster.ViewportZNearClipTestEnable = pipeline->depth_clip_enable;
-#elif GFX_VER == 8
- raster.ViewportZClipTestEnable = pipeline->depth_clip_enable;
-#endif
-#if GFX_VER >= 9
raster.ConservativeRasterizationEnable =
rs->conservative_mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
-#endif
GENX(3DSTATE_SF_pack)(NULL, pipeline->gfx8.sf, &sf);
GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gfx8.raster, &raster);
hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold;
#endif
-#if GFX_VER >= 9
hs.DispatchMode = tcs_prog_data->base.dispatch_mode;
hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id;
-#endif
}
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_TE), te) {
gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
- if (GFX_VER == 8) {
- /* Broadwell is weird. It needs us to divide by 2. */
- gs.MaximumNumberofThreads = devinfo->max_gs_threads / 2 - 1;
- } else {
- gs.MaximumNumberofThreads = devinfo->max_gs_threads - 1;
- }
+ gs.MaximumNumberofThreads = devinfo->max_gs_threads - 1;
gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
gs.OutputTopology = gs_prog_data->output_topology;
* Since 16x MSAA is first introduced on SKL, we don't need to apply
* the workaround on any older hardware.
*/
- if (GFX_VER >= 9 && !wm_prog_data->persample_dispatch &&
+ if (!wm_prog_data->persample_dispatch &&
ms != NULL && ms->rasterization_samples == 16) {
assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable);
ps._32PixelDispatchEnable = false;
ps.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
POSOFFSET_SAMPLE: POSOFFSET_NONE;
- ps.MaximumNumberofThreadsPerPSD =
- devinfo->max_threads_per_psd - (GFX_VER == 8 ? 2 : 1);
+ ps.MaximumNumberofThreadsPerPSD = devinfo->max_threads_per_psd - 1;
ps.DispatchGRFStartRegisterForConstantSetupData0 =
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
rp->stencil_self_dependency ||
wm_prog_data->uses_kill;
-#if GFX_VER >= 9
ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
ps.PixelShaderPullsBary = wm_prog_data->pulls_bary;
ps.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
else
ps.InputCoverageMaskState = ICMS_NORMAL;
-#else
- ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
-#endif
#if GFX_VER >= 11
ps.PixelShaderRequiresSourceDepthandorWPlaneCoefficients =
#if GFX_VER < 11
vfe.ResetGatewayTimer = true;
#endif
-#if GFX_VER == 8
- vfe.BypassGatewayControl = true;
-#endif
vfe.URBEntryAllocationSize = 2;
vfe.CURBEAllocationSize = vfe_curbe_allocation;
};
anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
-#if GFX_VER >= 9
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
-#endif
ps.PipelineSelection = _3D;
}
rect.DrawingRectangleOriginX = 0;
}
-#if GFX_VER >= 8
anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
genX(emit_sample_pattern)(&batch, NULL);
* number of GPU hangs on ICL.
*/
anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
-#endif
#if GFX_VER == 11
/* The default behavior of bit 5 "Headerless Message for Pre-emptable
*
* This is only safe on kernels with context isolation support.
*/
- if (GFX_VER >= 8 && device->physical->has_context_isolation) {
-#if GFX_VER >= 9
+ if (device->physical->has_context_isolation) {
anv_batch_write_reg(&batch, GENX(CS_DEBUG_MODE2), csdm2) {
csdm2.CONSTANT_BUFFERAddressOffsetDisable = true;
csdm2.CONSTANT_BUFFERAddressOffsetDisableMask = true;
}
-#elif GFX_VER == 8
- anv_batch_write_reg(&batch, GENX(INSTPM), instpm) {
- instpm.CONSTANT_BUFFERAddressOffsetDisable = true;
- instpm.CONSTANT_BUFFERAddressOffsetDisableMask = true;
- }
-#endif
}
init_common_queue_state(queue, &batch);
batch.end = (void *) cmds + sizeof(cmds);
anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
-#if GFX_VER >= 9
ps.MaskBits = 3;
-#endif
#if GFX_VER >= 11
ps.MaskBits |= 0x10;
ps.MediaSamplerDOPClockGateEnable = true;
ms.NumberofMultisamples = __builtin_ffs(samples) - 1;
ms.PixelLocation = CENTER;
-#if GFX_VER >= 8
+
/* The PRM says that this bit is valid only for DX9:
*
* SW can choose to set this bit only for DX9 API. DX10/OGL API's
* should not have any effect by setting or not setting this bit.
*/
ms.PixelPositionOffsetEnable = false;
-#else
- switch (samples) {
- case 1:
- INTEL_SAMPLE_POS_1X_ARRAY(ms.Sample, sl->locations);
- break;
- case 2:
- INTEL_SAMPLE_POS_2X_ARRAY(ms.Sample, sl->locations);
- break;
- case 4:
- INTEL_SAMPLE_POS_4X_ARRAY(ms.Sample, sl->locations);
- break;
- case 8:
- INTEL_SAMPLE_POS_8X_ARRAY(ms.Sample, sl->locations);
- break;
- default:
- break;
- }
-#endif
}
}
-#if GFX_VER >= 8
void
genX(emit_sample_pattern)(struct anv_batch *batch,
const struct vk_sample_locations_state *sl)
* lit sample and that it's the same for all samples in a pixel; they
* have no requirement that it be the one closest to center.
*/
- for (uint32_t i = 1; i <= (GFX_VER >= 9 ? 16 : 8); i *= 2) {
+ for (uint32_t i = 1; i <= 16; i *= 2) {
switch (i) {
case VK_SAMPLE_COUNT_1_BIT:
if (sl && sl->per_pixel == i) {
INTEL_SAMPLE_POS_8X(sp._8xSample);
}
break;
-#if GFX_VER >= 9
case VK_SAMPLE_COUNT_16_BIT:
if (sl && sl->per_pixel == i) {
INTEL_SAMPLE_POS_16X_ARRAY(sp._16xSample, sl->locations);
INTEL_SAMPLE_POS_16X(sp._16xSample);
}
break;
-#endif
default:
unreachable("Invalid sample count");
}
}
}
}
-#endif
#if GFX_VER >= 11
void
[VK_COMPARE_OP_ALWAYS] = PREFILTEROP_NEVER,
};
-#if GFX_VER >= 9
static const uint32_t vk_to_intel_sampler_reduction_mode[] = {
[VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE] = STD_FILTER,
[VK_SAMPLER_REDUCTION_MODE_MIN] = MINIMUM,
[VK_SAMPLER_REDUCTION_MODE_MAX] = MAXIMUM,
};
-#endif
VkResult genX(CreateSampler)(
VkDevice _device,
border_color_offset = sampler->custom_border_color.offset;
}
-#if GFX_VER >= 9
unsigned sampler_reduction_mode = STD_FILTER;
bool enable_sampler_reduction = false;
-#endif
vk_foreach_struct_const(ext, pCreateInfo->pNext) {
switch (ext->sType) {
sampler->conversion = conversion;
break;
}
-#if GFX_VER >= 9
case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: {
VkSamplerReductionModeCreateInfo *sampler_reduction =
(VkSamplerReductionModeCreateInfo *) ext;
enable_sampler_reduction = true;
break;
}
-#endif
case VK_STRUCTURE_TYPE_SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT: {
VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
(VkSamplerCustomBorderColorCreateInfoEXT *) ext;
.LODPreClampMode = CLAMP_MODE_OGL,
-#if GFX_VER == 8
- .BaseMipLevel = 0.0,
-#endif
.MipModeFilter = mip_filter_mode,
.MagModeFilter = vk_to_intel_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
.MinModeFilter = vk_to_intel_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
.TCYAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeV],
.TCZAddressControlMode = vk_to_intel_tex_address[pCreateInfo->addressModeW],
-#if GFX_VER >= 9
.ReductionType = sampler_reduction_mode,
.ReductionTypeEnable = enable_sampler_reduction,
-#endif
};
GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
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