Convert CONFIG_SYS_BOOK3E_HV to Kconfig
authorTom Rini <trini@konsulko.com>
Sat, 25 Jun 2022 15:02:43 +0000 (11:02 -0400)
committerTom Rini <trini@konsulko.com>
Thu, 7 Jul 2022 13:29:56 +0000 (09:29 -0400)
This converts the following to Kconfig:
   CONFIG_SYS_BOOK3E_HV

Signed-off-by: Tom Rini <trini@konsulko.com>
49 files changed:
arch/powerpc/cpu/mpc85xx/Kconfig
configs/P2041RDB_NAND_defconfig
configs/P2041RDB_SDCARD_defconfig
configs/P2041RDB_SPIFLASH_defconfig
configs/P2041RDB_defconfig
configs/P3041DS_NAND_defconfig
configs/P3041DS_SDCARD_defconfig
configs/P3041DS_SPIFLASH_defconfig
configs/P3041DS_defconfig
configs/P4080DS_SDCARD_defconfig
configs/P4080DS_SPIFLASH_defconfig
configs/P4080DS_defconfig
configs/P5040DS_NAND_defconfig
configs/P5040DS_SDCARD_defconfig
configs/P5040DS_SPIFLASH_defconfig
configs/P5040DS_defconfig
configs/T1024RDB_NAND_defconfig
configs/T1024RDB_SDCARD_defconfig
configs/T1024RDB_SPIFLASH_defconfig
configs/T1024RDB_defconfig
configs/T1042D4RDB_NAND_defconfig
configs/T1042D4RDB_SDCARD_defconfig
configs/T1042D4RDB_SPIFLASH_defconfig
configs/T1042D4RDB_defconfig
configs/T2080QDS_NAND_defconfig
configs/T2080QDS_SDCARD_defconfig
configs/T2080QDS_SECURE_BOOT_defconfig
configs/T2080QDS_SPIFLASH_defconfig
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
configs/T2080QDS_defconfig
configs/T2080RDB_NAND_defconfig
configs/T2080RDB_SDCARD_defconfig
configs/T2080RDB_SPIFLASH_defconfig
configs/T2080RDB_defconfig
configs/T2080RDB_revD_NAND_defconfig
configs/T2080RDB_revD_SDCARD_defconfig
configs/T2080RDB_revD_SPIFLASH_defconfig
configs/T2080RDB_revD_defconfig
configs/T4240RDB_SDCARD_defconfig
configs/T4240RDB_defconfig
configs/kmcent2_defconfig
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/corenet_ds.h
include/configs/kmcent2.h

index e7003d3..f4f5ebf 100644 (file)
@@ -1216,6 +1216,10 @@ config SYS_FSL_LBC_CLK_DIV
 config ENABLE_36BIT_PHYS
        bool "Enable 36bit physical address space support"
 
+config SYS_BOOK3E_HV
+       bool "Category E.HV is supported"
+       depends on BOOKE
+
 config SYS_MPC85XX_NO_RESETVEC
        bool "Discard resetvec section and move bootpg section up"
        depends on MPC85xx
index 5063470..459b9e6 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index a64f892..6ff6a42 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index f295174..a5872fa 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index e3dd1e9..247db8e 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 3e4cb51..91ad3ee 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 66eb6c3..6ca91fe 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 87c62be..13857b8 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index d083c25..b587d52 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index ed6f3de..c88a869 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index e77085a..a627475 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 91aa75d..82371ea 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 3a48362..be3d388 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 9aa293d..4dcdb39 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 6f0d51a..7620f48 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index ae5f7b7..68573a5 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index ad33aa8..d10799f 100644 (file)
@@ -13,6 +13,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
index 06bb7b7..22c404e 100644 (file)
@@ -14,6 +14,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
index f88fb38..2f1e9ca 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
index a0908ac..5c30e9f 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index bb32ddf..00ea217 100644 (file)
@@ -12,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
index 932a4e1..c738e9c 100644 (file)
@@ -13,6 +13,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
index 0c4e339..bc38fa6 100644 (file)
@@ -15,6 +15,7 @@ CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
index 4445801..af7df9e 100644 (file)
@@ -8,6 +8,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 05e46e6..e7ce363 100644 (file)
@@ -19,6 +19,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
index 1818762..a2a2c58 100644 (file)
@@ -20,6 +20,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
index 30d1b85..4f35dbd 100644 (file)
@@ -6,6 +6,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_NXP_ESBC=y
 CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
 CONFIG_PCIE1=y
index 73c50b9..b02939f 100644 (file)
@@ -22,6 +22,7 @@ CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
index 48ef69c..6caffde 100644 (file)
@@ -9,6 +9,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SRIO_PCIE_BOOT_SLAVE=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
index a94fd3f..4ec70d6 100644 (file)
@@ -10,6 +10,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
index 6566226..f382288 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
index 3333ac1..5837b3d 100644 (file)
@@ -17,6 +17,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
index 5812daa..ab191c7 100644 (file)
@@ -19,6 +19,7 @@ CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
index 563d0b5..fff8a26 100644 (file)
@@ -12,8 +12,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
-<<<<<<< HEAD
-=======
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
@@ -22,7 +21,6 @@ CONFIG_VID=y
 CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
 CONFIG_VOL_MONITOR_IR36021_READ=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
->>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_SYS_MEMTEST_START=0x00200000
 CONFIG_SYS_MEMTEST_END=0x00400000
 CONFIG_MP=y
index 9844343..c5ab7af 100644 (file)
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
index 004f677..83f4725 100644 (file)
@@ -17,6 +17,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
 <<<<<<< HEAD
index 610f3f8..0c53652 100644 (file)
@@ -19,6 +19,7 @@ CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
 <<<<<<< HEAD
index ca6a741..66a9d5d 100644 (file)
@@ -12,6 +12,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_T2080RDB_REV_D=y
 <<<<<<< HEAD
 =======
index 3e43f9b..639cb80 100644 (file)
@@ -17,6 +17,7 @@ CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 <<<<<<< HEAD
 =======
index 9f6457f..6f40361 100644 (file)
@@ -12,8 +12,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
-<<<<<<< HEAD
-=======
+CONFIG_SYS_BOOK3E_HV=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_PCIE3=y
@@ -22,7 +21,6 @@ CONFIG_VID=y
 CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
 CONFIG_VOL_MONITOR_IR36021_READ=y
 CONFIG_VOL_MONITOR_IR36021_SET=y
->>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
 CONFIG_MP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index cd6fb96..38d33c2 100644 (file)
@@ -11,6 +11,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_PCIE1=y
 CONFIG_KM_DEF_NETDEV="eth2"
index e019c16..2dc7da6 100644 (file)
@@ -25,7 +25,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
index a519b5a..159002d 100644 (file)
@@ -14,7 +14,6 @@
 #include <linux/stringify.h>
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
index 3a7c643..25d82db 100644 (file)
@@ -53,7 +53,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
index eff22c1..969e7f7 100644 (file)
@@ -21,7 +21,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV   /* Category E.HV supported */
 
 #define CONFIG_SYS_FSL_CPC     /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC     CONFIG_SYS_NUM_DDR_CTLRS
index ba9bfdd..0981259 100644 (file)
@@ -16,7 +16,6 @@
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV   /* Category E.HV supported */
 
 #define CONFIG_SYS_FSL_CPC     /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC     CONFIG_SYS_NUM_DDR_CTLRS
index 12b479f..6ec3c6a 100644 (file)
@@ -34,7 +34,6 @@
 #endif /* CONFIG_RAMBOOT_PBL */
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
index 2252bf8..d8ad456 100644 (file)
@@ -28,7 +28,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 
 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
index ed24733..eafdc35 100644 (file)
 #define KM_I2C_DEBLOCK_SDA     21
 
 /* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 
 #define CONFIG_RESET_VECTOR_ADDRESS    0xebfffffc