#define APCI3120_RD_FIFO 0x00
-/* status register bits */
-#define APCI3120_EOC 0x8000
-#define APCI3120_EOS 0x2000
-
/* software trigger dummy register */
#define APCI3120_START_CONVERSION 0x02
#define APCI3120_TIMER_DISABLE 0
#define APCI3120_TIMER_ENABLE 1
-#define APCI3120_FC_TIMER 0x1000
-
#define APCI3120_COUNTER 3
static int apci3120_setup_chan_list(struct comedi_device *dev,
unsigned int status;
status = inw(dev->iobase + APCI3120_STATUS_REG);
- if ((status & APCI3120_EOC) == 0)
+ if ((status & APCI3120_STATUS_EOC_INT) == 0)
return 0;
return -EBUSY;
}
struct apci3120_private *devpriv = dev->private;
struct comedi_subdevice *s = dev->read_subdev;
struct comedi_cmd *cmd = &s->async->cmd;
- unsigned short int_daq;
+ unsigned int status;
unsigned int int_amcc;
- int_daq = inw(dev->iobase + APCI3120_STATUS_REG) & 0xf000;
+ status = inw(dev->iobase + APCI3120_STATUS_REG);
int_amcc = inl(devpriv->amcc + AMCC_OP_REG_INTCSR);
- if ((!int_daq) && (!(int_amcc & ANY_S593X_INT))) {
+ if (!(status & APCI3120_STATUS_INT_MASK) &&
+ !(int_amcc & ANY_S593X_INT)) {
dev_err(dev->class_dev, "IRQ from unknown source\n");
return IRQ_NONE;
}
outl(int_amcc | 0x00ff0000, devpriv->amcc + AMCC_OP_REG_INTCSR);
- int_daq = (int_daq >> 12) & 0xF;
-
if (devpriv->b_ExttrigEnable == APCI3120_ENABLE) {
apci3120_exttrig_enable(dev, false);
devpriv->b_ExttrigEnable = APCI3120_DISABLE;
if (int_amcc & TARGET_ABORT_INT)
dev_err(dev->class_dev, "AMCC IRQ - TARGET DMA ABORT!\n");
- /* Ckeck if EOC interrupt */
- if (((int_daq & 0x8) == 0) &&
- (devpriv->b_InterruptMode == APCI3120_EOC_MODE)) {
+ if ((status & APCI3120_STATUS_EOC_INT) == 0 &&
+ devpriv->b_InterruptMode == APCI3120_EOC_MODE) {
/* nothing to do... EOC mode is not currently used */
}
- /* Check If EOS interrupt */
- if ((int_daq & 0x2) && (devpriv->b_InterruptMode == APCI3120_EOS_MODE)) {
+ if ((status & APCI3120_STATUS_EOS_INT) &&
+ devpriv->b_InterruptMode == APCI3120_EOS_MODE) {
if (devpriv->ai_running) {
unsigned short val;
int i;
}
}
- /* Timer2 interrupt */
- if (int_daq & 0x1) {
-
+ if (status & APCI3120_STATUS_TIMER2_INT) {
switch (devpriv->b_Timer2Mode) {
case APCI3120_COUNTER:
devpriv->mode &= ~APCI3120_MODE_EOS_IRQ_ENA;
apci3120_clr_timer2_interrupt(dev);
}
- if ((int_daq & 0x4) && (devpriv->b_InterruptMode == APCI3120_DMA_MODE)) {
+ if ((status & APCI3120_STATUS_AMCC_INT) &&
+ devpriv->b_InterruptMode == APCI3120_DMA_MODE) {
if (devpriv->ai_running) {
/* Clear Timer Write TC int */
unsigned int *data)
{
struct apci3120_private *devpriv = dev->private;
- unsigned short us_StatusValue;
+ unsigned int status;
if ((devpriv->b_Timer2Mode != APCI3120_WATCHDOG)
&& (devpriv->b_Timer2Mode != APCI3120_TIMER)) {
}
if (devpriv->b_Timer2Mode == APCI3120_TIMER) {
data[0] = apci3120_timer_read(dev, 2);
- } else { /* Read watch dog status */
- us_StatusValue = inw(dev->iobase + APCI3120_STATUS_REG);
- us_StatusValue =
- ((us_StatusValue & APCI3120_FC_TIMER) >> 12) & 1;
- if (us_StatusValue == 1)
+ } else {
+ /* Read watch dog status */
+ status = inw(dev->iobase + APCI3120_STATUS_REG);
+ if (status & APCI3120_STATUS_TIMER2_INT) {
apci3120_clr_timer2_interrupt(dev);
- data[0] = us_StatusValue; /* when data[0] = 1 then the watch dog has rundown */
+ data[0] = 1;
+ } else {
+ data[0] = 0;
+ }
}
return insn->n;
}
struct comedi_insn *insn,
unsigned int *data)
{
- unsigned int val;
+ unsigned int status;
- /* the input channels are bits 11:8 of the status reg */
- val = inw(dev->iobase + APCI3120_STATUS_REG);
- data[1] = (val >> 8) & 0xf;
+ status = inw(dev->iobase + APCI3120_STATUS_REG);
+ data[1] = APCI3120_STATUS_TO_DI_BITS(status);
return insn->n;
}
unsigned int status;
status = inw(dev->iobase + APCI3120_STATUS_REG);
- if (status & 0x0001) /* waiting for DA_READY */
+ if (status & APCI3120_STATUS_DA_READY)
return 0;
return -EBUSY;
}
#define APCI3120_CTRL_PR(x) (((x) & 0xf) << 8)
#define APCI3120_CTRL_PA(x) (((x) & 0xf) << 0)
#define APCI3120_STATUS_REG 0x02
+#define APCI3120_STATUS_EOC_INT (1 << 15)
+#define APCI3120_STATUS_AMCC_INT (1 << 14)
+#define APCI3120_STATUS_EOS_INT (1 << 13)
+#define APCI3120_STATUS_TIMER2_INT (1 << 12)
+#define APCI3120_STATUS_INT_MASK (0xf << 12)
+#define APCI3120_STATUS_TO_DI_BITS(x) (((x) >> 8) & 0xf)
#define APCI3120_STATUS_TO_VERSION(x) (((x) >> 4) & 0xf)
+#define APCI3120_STATUS_FIFO_FULL (1 << 2)
+#define APCI3120_STATUS_FIFO_EMPTY (1 << 1)
+#define APCI3120_STATUS_DA_READY (1 << 0)
#define APCI3120_TIMER_REG 0x04
#define APCI3120_CHANLIST_REG 0x06
#define APCI3120_CHANLIST_INDEX(x) (((x) & 0xf) << 8)