arm64: a37xx: pinctrl: Add missing pinmuxes into the list

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index e0445e3..d2abe67 100644 (file)
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -109,6 +109,16 @@ struct armada_37xx_pinctrl {
                .funcs = {_func1, _func2}       \
        }
 
+#define PIN_GRP_GPIO_0(_name, _start, _nr)     \
+       {                                       \
+               .name = _name,                  \
+               .start_pin = _start,            \
+               .npins = _nr,                   \
+               .reg_mask = 0,                  \
+               .val = {0},                     \
+               .funcs = {"gpio"}               \
+       }
+
 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1)        \
        {                                       \
                .name = _name,                  \
@@ -166,6 +176,7 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
                       "pwm", "led"),
        PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
        PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
+       PIN_GRP_GPIO_0("gpio1_5", 5, 1),
        PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
        PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
        PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
@@ -182,10 +193,13 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
        PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
        PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
+       PIN_GRP_GPIO_0("gpio2_2", 2, 1),
        PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
        PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
        PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
-       PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
+       PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
+       PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
+       PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
        PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
        PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
        PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),