[docs][RISCV] Remove outdated note about zfa implementation status
authorAlex Bradbury <asb@igalia.com>
Wed, 5 Apr 2023 13:52:08 +0000 (14:52 +0100)
committerAlex Bradbury <asb@igalia.com>
Wed, 5 Apr 2023 13:53:14 +0000 (14:53 +0100)
MC layer and codegen support for fli.{h,s,d} has since been implemented.

llvm/docs/RISCVUsage.rst

index c5ca207..2a9321c 100644 (file)
@@ -188,7 +188,7 @@ The primary goal of experimental support is to assist in the process of ratifica
   LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_.
 
 ``experimental-zfa``
-  LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). Load-immediate instructions (fli.s/fli.d/fli.h) haven't been implemented yet.
+  LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25).
 
 ``experimental-zicond``
   LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1`>_.