// picture level programing
gen8_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
- BEGIN_BCS_BATCH(batch, 2);
- OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
+ BEGIN_BCS_BATCH(batch, 3);
+ OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
OUT_BCS_RELOC(batch,
slice_batch_bo,
I915_GEM_DOMAIN_COMMAND, 0,
0);
+ OUT_BCS_BATCH(batch, 0);
ADVANCE_BCS_BATCH(batch);
// end programing
intel_batchbuffer_start_atomic(batch, 0x1000);
gen8_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
- BEGIN_BATCH(batch, 2);
- OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
+ BEGIN_BATCH(batch, 3);
+ OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
OUT_RELOC(batch,
vme_context->vme_batchbuffer.bo,
I915_GEM_DOMAIN_COMMAND, 0,
0);
+ OUT_BATCH(batch, 0);
ADVANCE_BATCH(batch);
intel_batchbuffer_end_atomic(batch);
dri_bo_unmap(command_buffer);
- BEGIN_BATCH(batch, 2);
- OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
- OUT_RELOC(batch, command_buffer,
+ if (IS_GEN8(i965->intel.device_id)) {
+ BEGIN_BATCH(batch, 3);
+ OUT_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
+ OUT_RELOC(batch, command_buffer,
I915_GEM_DOMAIN_COMMAND, 0,
0);
- ADVANCE_BATCH(batch);
+ OUT_BATCH(batch, 0);
+ ADVANCE_BATCH(batch);
+ } else {
+ BEGIN_BATCH(batch, 2);
+ OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
+ OUT_RELOC(batch, command_buffer,
+ I915_GEM_DOMAIN_COMMAND, 0,
+ 0);
+ ADVANCE_BATCH(batch);
+ }
dri_bo_unreference(command_buffer);