[llvm-mca][RISCV] Add RISCV-SEW instrument

Now that RISCV pseudo instructions now account for SEW in some cases,
it useful that RISCV SEW instruments exist so that llvm-mca can use
the SEW specific scheduler classes.

Differential Revision: https://reviews.llvm.org/D154142

diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index 13e2395..8f8684e 100644 (file)
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -69,26 +69,56 @@ uint8_t RISCVLMULInstrument::getLMUL() const {
       .Case("MF8", 0b111);
 }
 
+const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW";
+
+bool RISCVSEWInstrument::isDataValid(llvm::StringRef Data) {
+  // Return true if not one of the valid SEW strings
+  return StringSwitch<bool>(Data)
+      .Cases("E8", "E16", "E32", "E64", true)
+      .Default(false);
+}
+
+uint8_t RISCVSEWInstrument::getSEW() const {
+  // assertion prevents us from needing llvm_unreachable in the StringSwitch
+  // below
+  assert(isDataValid(getData()) && "Cannot get SEW because invalid Data value");
+  // These are the LMUL values that are used in RISC-V tablegen
+  return StringSwitch<uint8_t>(getData())
+      .Case("E8", 8)
+      .Case("E16", 16)
+      .Case("E32", 32)
+      .Case("E64", 64);
+}
+
 bool RISCVInstrumentManager::supportsInstrumentType(
     llvm::StringRef Type) const {
-  // Currently, only support for RISCVLMULInstrument type
-  return Type == RISCVLMULInstrument::DESC_NAME;
+  return Type == RISCVLMULInstrument::DESC_NAME ||
+         Type == RISCVSEWInstrument::DESC_NAME;
 }
 
 UniqueInstrument
 RISCVInstrumentManager::createInstrument(llvm::StringRef Desc,
                                          llvm::StringRef Data) {
-  if (Desc != RISCVLMULInstrument::DESC_NAME) {
-    LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc
-                      << '\n');
-    return nullptr;
+  if (Desc == RISCVLMULInstrument::DESC_NAME) {
+    if (!RISCVLMULInstrument::isDataValid(Data)) {
+      LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
+                        << Data << '\n');
+      return nullptr;
+    }
+    return std::make_unique<RISCVLMULInstrument>(Data);
   }
-  if (!RISCVLMULInstrument::isDataValid(Data)) {
-    LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
-                      << Data << '\n');
-    return nullptr;
+
+  if (Desc == RISCVSEWInstrument::DESC_NAME) {
+    if (!RISCVSEWInstrument::isDataValid(Data)) {
+      LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
+                        << Data << '\n');
+      return nullptr;
+    }
+    return std::make_unique<RISCVSEWInstrument>(Data);
   }
-  return std::make_unique<RISCVLMULInstrument>(Data);
+
+  LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc << '\n');
+  return nullptr;
 }
 
 SmallVector<UniqueInstrument>
@@ -129,6 +159,28 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
     SmallVector<UniqueInstrument> Instruments;
     Instruments.emplace_back(
         createInstrument(RISCVLMULInstrument::DESC_NAME, LMUL));
+
+    unsigned SEW = RISCVVType::getSEW(VTypeI);
+    StringRef SEWStr;
+    switch (SEW) {
+    case 8:
+      SEWStr = "E8";
+      break;
+    case 16:
+      SEWStr = "E16";
+      break;
+    case 32:
+      SEWStr = "E32";
+      break;
+    case 64:
+      SEWStr = "E64";
+      break;
+    default:
+      llvm_unreachable("Cannot create instrument for SEW");
+    }
+    Instruments.emplace_back(
+        createInstrument(RISCVSEWInstrument::DESC_NAME, SEWStr));
+
     return Instruments;
   }
   return SmallVector<UniqueInstrument>();
@@ -140,36 +192,55 @@ unsigned RISCVInstrumentManager::getSchedClassID(
   unsigned short Opcode = MCI.getOpcode();
   unsigned SchedClassID = MCII.get(Opcode).getSchedClass();
 
-  for (const auto &I : IVec) {
-    // Unknown Instrument kind
-    if (I->getDesc() == RISCVLMULInstrument::DESC_NAME) {
-      uint8_t LMUL = static_cast<RISCVLMULInstrument *>(I)->getLMUL();
-      const RISCVVInversePseudosTable::PseudoInfo *RVV =
-          RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
-      // Not a RVV instr
-      if (!RVV) {
-        LLVM_DEBUG(
-            dbgs()
-            << "RVCB: Could not find PseudoInstruction for Opcode "
-            << MCII.getName(Opcode) << ", LMUL=" << I->getData()
-            << ". Ignoring instrumentation and using original SchedClassID="
-            << SchedClassID << '\n');
-        return SchedClassID;
-      }
-
-      // Override using pseudo
-      LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode "
-                        << MCII.getName(Opcode) << ", LMUL=" << I->getData()
-                        << ". Overriding original SchedClassID=" << SchedClassID
-                        << " with " << MCII.getName(RVV->Pseudo) << '\n');
-      return MCII.get(RVV->Pseudo).getSchedClass();
-    }
+  // Unpack all possible RISCV instruments from IVec.
+  RISCVLMULInstrument *LI = nullptr;
+  RISCVSEWInstrument *SI = nullptr;
+  for (auto &I : IVec) {
+    if (I->getDesc() == RISCVLMULInstrument::DESC_NAME)
+      LI = static_cast<RISCVLMULInstrument *>(I);
+    else if (I->getDesc() == RISCVSEWInstrument::DESC_NAME)
+      SI = static_cast<RISCVSEWInstrument *>(I);
+  }
+
+  // Need LMUL or LMUL, SEW in order to override opcode. If no LMUL is provided,
+  // then no option to override.
+  if (!LI) {
+    LLVM_DEBUG(
+        dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
+    return SchedClassID;
+  }
+  uint8_t LMUL = LI->getLMUL();
+
+  // getBaseInfo works with (Opcode, LMUL, 0) if no SEW instrument,
+  // or (Opcode, LMUL, SEW) if SEW instrument is active, and depends on LMUL
+  // and SEW, or (Opcode, LMUL, 0) if does not depend on SEW.
+  uint8_t SEW = SI ? SI->getSEW() : 0;
+  // Check if it depends on LMUL and SEW
+  const RISCVVInversePseudosTable::PseudoInfo *RVV =
+      RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
+  // Check if it depends only on LMUL
+  if (!RVV)
+    RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
+
+  // Not a RVV instr
+  if (!RVV) {
+    LLVM_DEBUG(
+        dbgs() << "RVCB: Could not find PseudoInstruction for Opcode "
+               << MCII.getName(Opcode)
+               << ", LMUL=" << (LI ? LI->getData() : "Unspecified")
+               << ", SEW=" << (SI ? SI->getData() : "Unspecified")
+               << ". Ignoring instrumentation and using original SchedClassID="
+               << SchedClassID << '\n');
+    return SchedClassID;
   }
 
-  // Unknown Instrument kind
-  LLVM_DEBUG(
-      dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
-  return SchedClassID;
+  // Override using pseudo
+  LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode "
+                    << MCII.getName(Opcode) << ", LMUL=" << LI->getData()
+                    << ", SEW=" << (SI ? SI->getData() : "Unspecified")
+                    << ". Overriding original SchedClassID=" << SchedClassID
+                    << " with " << MCII.getName(RVV->Pseudo) << '\n');
+  return MCII.get(RVV->Pseudo).getSchedClass();
 }
 
 } // namespace mca

diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
index 8e4c00b..34efa0b 100644 (file)
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
@@ -31,13 +31,25 @@ public:
   static const StringRef DESC_NAME;
   static bool isDataValid(StringRef Data);
 
-  RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
+  explicit RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
 
   ~RISCVLMULInstrument() = default;
 
   uint8_t getLMUL() const;
 };
 
+class RISCVSEWInstrument : public Instrument {
+public:
+  static const StringRef DESC_NAME;
+  static bool isDataValid(StringRef Data);
+
+  explicit RISCVSEWInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
+
+  ~RISCVSEWInstrument() = default;
+
+  uint8_t getSEW() const;
+};
+
 class RISCVInstrumentManager : public InstrumentManager {
 public:
   RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)

diff --git a/llvm/test/tools/llvm-mca/RISCV/different-instruments.s b/llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/different-instruments.s
rename to llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s b/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
new file mode 100644 (file)
index 0000000..810b383
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
@@ -0,0 +1,74 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+# LLVM-MCA-RISCV-SEW E8
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      4
+# CHECK-NEXT: Total Cycles:      358
+# CHECK-NEXT: Total uOps:        4
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 354.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     2.00    -     354.00 354.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli     zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s
rename to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s
rename to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s
rename to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s
rename to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s b/llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s
rename to llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s b/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s
new file mode 100644 (file)
index 0000000..08339ad
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s
@@ -0,0 +1,91 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+vdivu.vv v8, v8, v12
+vsetvli zero, a0, e32, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E32
+vdiv.vv v8, v8, v12
+vdivu.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      8
+# CHECK-NEXT: Total Cycles:      570
+# CHECK-NEXT: Total uOps:        8
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 566.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      114   114.00                      vdivu.vv       v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e32, m1, tu, mu
+# CHECK-NEXT:  1      112   112.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      112   112.00                      vdivu.vv       v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     3.00    -     566.00 566.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdivu.vv v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     112.00 112.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -      -      -     112.00 112.00  -      -     vdivu.vv v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli     zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 4.     1     0.0    0.0    0.0       vdivu.vv    v8, v8, v12
+# CHECK-NEXT: 5.     1     0.0    0.0    0.0       vsetvli     zero, a0, e32, m1, tu, mu
+# CHECK-NEXT: 6.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 7.     1     0.0    0.0    0.0       vdivu.vv    v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s b/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s
new file mode 100644 (file)
index 0000000..2864e6c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+# Test LMUL but no SEW falls back to worst case.
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vdiv.vv v8, v8, v12
+# LLVM-MCA-RISCV-SEW E8
+vdiv.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      3
+# CHECK-NEXT: Total Cycles:      484
+# CHECK-NEXT: Total uOps:        3
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 480.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     480.00 480.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s b/llvm/test/tools/llvm-mca/RISCV/riscv-lmul-instrument-no-data-is-err.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s
rename to llvm/test/tools/llvm-mca/RISCV/riscv-lmul-instrument-no-data-is-err.s

diff --git a/llvm/test/tools/llvm-mca/RISCV/riscv-sew-instrument-no-data-is-err.s b/llvm/test/tools/llvm-mca/RISCV/riscv-sew-instrument-no-data-is-err.s
new file mode 100644 (file)
index 0000000..7076f92
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/riscv-sew-instrument-no-data-is-err.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-SEW
+vdiv.vv v8, v8, v12
+
+# CHECK: error: Failed to create RISCV-SEW instrument with no data
+# CHECK: # LLVM-MCA-RISCV-SEW
+# CHECK:  ^
+# CHECK: error: There was an error parsing comments.

diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s
new file mode 100644 (file)
index 0000000..19fe178
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+# LLVM-MCA-RISCV-SEW E8
+vdiv.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      244
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 240.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     240.00 240.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s
new file mode 100644 (file)
index 0000000..79f0d27
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+# llvm-mca should use `WorstCase` SEW if there is no instrument that specifies
+# which SEW to use. On sifive-x280, `WorstCase` SEW is the smallest SEW, so
+# the first vadd.vv should use E8 and the second should use E64.
+
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e8, m8, tu, mu
+# LLVM-MCA-RISCV-LMUL M8
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      3
+# CHECK-NEXT: Total Cycles:      2833
+# CHECK-NEXT: Total uOps:        3
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.00
+# CHECK-NEXT: IPC:               0.00
+# CHECK-NEXT: Block RThroughput: 2832.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      1920   1920.00                      vdiv.vv      v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  1      912   912.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     2832.00 2832.00  -    -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -      -      -     1920.00 1920.00  -    -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     912.00 912.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s
new file mode 100644 (file)
index 0000000..4f62578
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN foo
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+# LLVM-MCA-END foo
+
+# CHECK:      [0] Code Region - foo
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      118
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.02
+# CHECK-NEXT: IPC:               0.02
+# CHECK-NEXT: Block RThroughput: 114.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     114.00 114.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s
new file mode 100644 (file)
index 0000000..12d4bb4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN foo
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+# LLVM-MCA-END foo
+vdiv.vv v8, v8, v12
+
+# CHECK:      [0] Code Region - foo
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      118
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.02
+# CHECK-NEXT: IPC:               0.02
+# CHECK-NEXT: Block RThroughput: 114.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     114.00 114.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s b/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
index ef08018..3a996e9 100644 (file)
--- a/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
+++ b/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
@@ -1,10 +1,10 @@
 # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-V MF9
+# LLVM-MCA-RISCV-LMUL MF9
 vadd.vv v12, v12, v12
 
-# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V
-# CHECK: # LLVM-MCA-RISCV-V MF9
+# CHECK: error: Failed to create RISCV-LMUL instrument with data: MF9
+# CHECK: # LLVM-MCA-RISCV-LMUL MF9
 # CHECK:  ^
 # CHECK:  error: There was an error parsing comments.

diff --git a/llvm/test/tools/llvm-mca/RISCV/unknown-sew-is-err.s b/llvm/test/tools/llvm-mca/RISCV/unknown-sew-is-err.s
new file mode 100644 (file)
index 0000000..0a75eb4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/unknown-sew-is-err.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E99
+vdiv.vv v8, v8, v12
+
+# CHECK: error: Failed to create RISCV-SEW instrument with data: E99
+# CHECK: # LLVM-MCA-RISCV-SEW E99
+# CHECK:  ^
+# CHECK:  error: There was an error parsing comments.

diff --git a/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s b/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s
new file mode 100644 (file)
index 0000000..4830fb1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetivli zero, 8, e8, m1, tu, mu
+vdiv.vv v8, v8, v12
+vsetivli zero, 8, e32, m8, tu, mu
+vdiv.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      4
+# CHECK-NEXT: Total Cycles:      1140
+# CHECK-NEXT: Total uOps:        4
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.00
+# CHECK-NEXT: IPC:               0.00
+# CHECK-NEXT: Block RThroughput: 1136.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetivli       zero, 8, e8, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetivli       zero, 8, e32, m8, tu, mu
+# CHECK-NEXT:  1      896   896.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     2.00    -     1136.00 1136.00  -    -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetivli zero, 8, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetivli zero, 8, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     896.00 896.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetivli        zero, 8, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetivli    zero, 8, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetivli    zero, 8, e32, m8, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s b/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s
new file mode 100644 (file)
index 0000000..79d6d71
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e32, m8, tu, mu
+vdiv.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      4
+# CHECK-NEXT: Total Cycles:      1140
+# CHECK-NEXT: Total uOps:        4
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.00
+# CHECK-NEXT: IPC:               0.00
+# CHECK-NEXT: Block RThroughput: 1136.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv        v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e32, m8, tu, mu
+# CHECK-NEXT:  1      896   896.00                      vdiv.vv        v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     2.00    -     1136.00 1136.00  -    -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv  v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     896.00 896.00  -      -     vdiv.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli     zero, a0, e32, m8, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv     v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>