" */\n"
"\n"
"/**\n"
-" * \file sim_vector.h\n"
-" * \author Benjamin Segovia <benjamin.segovia@intel.com>\n"
+" * \\file sim_vector.h\n"
+" * \\author Benjamin Segovia <benjamin.segovia@intel.com>\n"
" *\n"
" * c++ class helper for the simulator\n"
" */\n"
"}\n"
"\n"
"/* Vector instructions that use sse* */\n"
-"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, INTRINSIC_NAME, FN, FN0, FN1)\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\n"
-" for (uint32_t i = 0; i < vectorNum; ++i)\\n"
-" dst.m[i] = FN(INTRINSIC_NAME(FN0(v0.m[i]), FN1(v1.m[i])));\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\n"
-" NAME(dst, v0, simd_dw<vectorNum>(v1));\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\n"
-" NAME(dst, simd_dw<vectorNum>(v0), v1);\\n"
+"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, INTRINSIC_NAME, FN, FN0, FN1)\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\\n"
+" for (uint32_t i = 0; i < vectorNum; ++i)\\\n"
+" dst.m[i] = FN(INTRINSIC_NAME(FN0(v0.m[i]), FN1(v1.m[i])));\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\\n"
+" NAME(dst, v0, simd_dw<vectorNum>(v1));\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\\n"
+" NAME(dst, simd_dw<vectorNum>(v0), v1);\\\n"
"}\n"
"VEC_OP(simd_dw<vectorNum>, simd_dw<vectorNum>, ADD_F, _mm_add_ps, ID, ID, ID);\n"
"VEC_OP(simd_dw<vectorNum>, simd_dw<vectorNum>, SUB_F, _mm_sub_ps, ID, ID, ID);\n"
"#undef VEC_OP\n"
"\n"
"/* Vector integer operations that we can get by switching argument order */\n"
-"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, INTRINSIC_NAME, FN, FN0, FN1)\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\n"
-" for (uint32_t i = 0; i < vectorNum; ++i)\\n"
-" dst.m[i] = _mm_xor_ps(FN(INTRINSIC_NAME(FN1(v0.m[i]), FN0(v1.m[i]))), alltrue.v);\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\n"
-" NAME(dst, v0, simd_dw<vectorNum>(v1));\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\n"
-" NAME(dst, simd_dw<vectorNum>(v0), v1);\\n"
+"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, INTRINSIC_NAME, FN, FN0, FN1)\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\\n"
+" for (uint32_t i = 0; i < vectorNum; ++i)\\\n"
+" dst.m[i] = _mm_xor_ps(FN(INTRINSIC_NAME(FN1(v0.m[i]), FN0(v1.m[i]))), alltrue.v);\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\\n"
+" NAME(dst, v0, simd_dw<vectorNum>(v1));\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\\n"
+" NAME(dst, simd_dw<vectorNum>(v0), v1);\\\n"
"}\n"
"VEC_OP(simd_m<vectorNum>, simd_dw<vectorNum>, GE_S32, _mm_cmplt_epi32, SI2PS, PS2SI, PS2SI);\n"
"VEC_OP(simd_m<vectorNum>, simd_dw<vectorNum>, LE_S32, _mm_cmpgt_epi32, SI2PS, PS2SI, PS2SI);\n"
"#undef VEC_OP\n"
"\n"
"/* Vector binary integer operations that require C */\n"
-"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, OP, FIELD)\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\n"
-" for (uint32_t i = 0; i < vectorNum; ++i) {\\n"
-" cast_dw c0(v0.m[i]), c1(v1.m[i]), d;\\n"
-" for (uint32_t j = 0; j < 4; ++j)\\n"
-" d.FIELD[j] = c0.FIELD[j] OP c1.FIELD[j];\\n"
-" dst.m[i] = d.v;\\n"
-" }\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\n"
-" NAME(dst, v0, simd_dw<vectorNum>(v1));\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\n"
-" NAME(dst, simd_dw<vectorNum>(v0), v1);\\n"
+"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, OP, FIELD)\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\\n"
+" for (uint32_t i = 0; i < vectorNum; ++i) {\\\n"
+" cast_dw c0(v0.m[i]), c1(v1.m[i]), d;\\\n"
+" for (uint32_t j = 0; j < 4; ++j)\\\n"
+" d.FIELD[j] = c0.FIELD[j] OP c1.FIELD[j];\\\n"
+" dst.m[i] = d.v;\\\n"
+" }\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\\n"
+" NAME(dst, v0, simd_dw<vectorNum>(v1));\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\\n"
+" NAME(dst, simd_dw<vectorNum>(v0), v1);\\\n"
"}\n"
"VEC_OP(simd_dw<vectorNum>, simd_dw<vectorNum>, MUL_S32, *, s);\n"
"VEC_OP(simd_dw<vectorNum>, simd_dw<vectorNum>, DIV_S32, /, s);\n"
"#undef VEC_OP\n"
"\n"
"/* Vector compare vectors that require C */\n"
-"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, OP, FIELD)\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\n"
-" for (uint32_t i = 0; i < vectorNum; ++i) {\\n"
-" cast_dw c0(v0.m[i]), c1(v1.m[i]), d;\\n"
-" for (uint32_t j = 0; j < 4; ++j)\\n"
-" d.u[j] = (c0.FIELD[j] OP c1.FIELD[j]) ? ~0u : 0u;\\n"
-" dst.m[i] = d.v;\\n"
-" }\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\n"
-" for (uint32_t i = 0; i < vectorNum; ++i) {\\n"
-" cast_dw c0(v0.m[i]), d;\\n"
-" for (uint32_t j = 0; j < 4; ++j)\\n"
-" d.u[j] = (c0.FIELD[j] OP v1.FIELD) ? ~0u : 0u;\\n"
-" dst.m[i] = d.v;\\n"
-" }\\n"
-"}\\n"
-"template <uint32_t vectorNum>\\n"
-"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\n"
-" for (uint32_t i = 0; i < vectorNum; ++i) {\\n"
-" cast_dw c1(v1.m[i]), d;\\n"
-" for (uint32_t j = 0; j < 4; ++j)\\n"
-" d.u[j] = (v0.FIELD OP c1.FIELD[j]) ? ~0u : 0u;\\n"
-" dst.m[i] = d.v;\\n"
-" }\\n"
+"#define VEC_OP(DST_TYPE, SRC_TYPE, NAME, OP, FIELD)\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const SRC_TYPE &v1) {\\\n"
+" for (uint32_t i = 0; i < vectorNum; ++i) {\\\n"
+" cast_dw c0(v0.m[i]), c1(v1.m[i]), d;\\\n"
+" for (uint32_t j = 0; j < 4; ++j)\\\n"
+" d.u[j] = (c0.FIELD[j] OP c1.FIELD[j]) ? ~0u : 0u;\\\n"
+" dst.m[i] = d.v;\\\n"
+" }\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const SRC_TYPE &v0, const scalar_dw &v1) {\\\n"
+" for (uint32_t i = 0; i < vectorNum; ++i) {\\\n"
+" cast_dw c0(v0.m[i]), d;\\\n"
+" for (uint32_t j = 0; j < 4; ++j)\\\n"
+" d.u[j] = (c0.FIELD[j] OP v1.FIELD) ? ~0u : 0u;\\\n"
+" dst.m[i] = d.v;\\\n"
+" }\\\n"
+"}\\\n"
+"template <uint32_t vectorNum>\\\n"
+"INLINE void NAME(DST_TYPE &dst, const scalar_dw &v0, const SRC_TYPE &v1) {\\\n"
+" for (uint32_t i = 0; i < vectorNum; ++i) {\\\n"
+" cast_dw c1(v1.m[i]), d;\\\n"
+" for (uint32_t j = 0; j < 4; ++j)\\\n"
+" d.u[j] = (v0.FIELD OP c1.FIELD[j]) ? ~0u : 0u;\\\n"
+" dst.m[i] = d.v;\\\n"
+" }\\\n"
"}\n"
"VEC_OP(simd_m<vectorNum>, simd_dw<vectorNum>, LE_U32, <=, u);\n"
"VEC_OP(simd_m<vectorNum>, simd_dw<vectorNum>, LT_U32, <, u);\n"