This is a series of patches that add support for the SPARC M7 cpu to

binutils.  They were discussed and approved here:

  https://sourceware.org/ml/binutils/2014-10/msg00038.html

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index dd59324..aa2f3ef 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): Handle
+       the hwcaps2 object attribute.
+
 2014-10-04  Alan Modra  <amodra@gmail.com>
 
        PR 17447

diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index 2a5eb01..d5f92d4 100644 (file)
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -4908,10 +4908,17 @@ _bfd_sparc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
 
   in_attr = &in_attrs[Tag_GNU_Sparc_HWCAPS];
   out_attr = &out_attrs[Tag_GNU_Sparc_HWCAPS];
+  
+  out_attr->i |= in_attr->i;
+  out_attr->type = 1;
 
+  in_attr = &in_attrs[Tag_GNU_Sparc_HWCAPS2];
+  out_attr = &out_attrs[Tag_GNU_Sparc_HWCAPS2];
+  
   out_attr->i |= in_attr->i;
   out_attr->type = 1;
 
+
   /* Merge Tag_compatibility attributes and any common GNU ones.  */
   _bfd_elf_merge_object_attributes (ibfd, obfd);
 

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index e8b2daf..34d65fc 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * readelf.c (display_sparc_hwcaps2): New function.
+       (display_sparc_gnu_attribute): Call `display_sparc_hwcaps2' when
+       handling `Tag_GNU_Sparc_HWCAPS2' attributes.
+
 2014-09-22  Alan Modra  <amodra@gmail.com>
 
        PR 16563

diff --git a/binutils/readelf.c b/binutils/readelf.c
index d9c12cc..3cf46d8 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -11977,22 +11977,64 @@ display_sparc_hwcaps (int mask)
   fputc('\n', stdout);
 }
 
+static void
+display_sparc_hwcaps2 (int mask)
+{
+  if (mask)
+    {
+      int first = 1;
+      if (mask & ELF_SPARC_HWCAP2_FJATHPLUS)
+       fputs ("fjathplus", stdout), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_VIS3B)
+       printf ("%svis3b", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_ADP)
+       printf ("%sadp", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_SPARC5)
+       printf ("%ssparc5", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_MWAIT)
+       printf ("%smwait", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_XMPMUL)
+       printf ("%sxmpmul", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_XMONT)
+       printf ("%sxmont2", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_NSEC)
+       printf ("%snsec", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_FJATHHPC)
+       printf ("%sfjathhpc", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_FJDES)
+       printf ("%sfjdes", first ? "" : "|"), first = 0;
+      if (mask & ELF_SPARC_HWCAP2_FJAES)
+       printf ("%sfjaes", first ? "" : "|"), first = 0;
+    }
+  else
+    fputc('0', stdout);
+  fputc('\n', stdout);
+}
+
 static unsigned char *
 display_sparc_gnu_attribute (unsigned char * p,
                             int tag,
                             const unsigned char * const end)
 {
+  unsigned int len;
+  int val;
+
   if (tag == Tag_GNU_Sparc_HWCAPS)
     {
-      unsigned int len;
-      int val;
-
       val = read_uleb128 (p, &len, end);
       p += len;
       printf ("  Tag_GNU_Sparc_HWCAPS: ");
       display_sparc_hwcaps (val);
       return p;
-   }
+    }
+  if (tag == Tag_GNU_Sparc_HWCAPS2)
+    {
+      val = read_uleb128 (p, &len, end);
+      p += len;
+      printf ("  Tag_GNU_Sparc_HWCAPS2: ");
+      display_sparc_hwcaps2 (val);
+      return p;
+    }
 
   return display_tag_value (tag, p, end);
 }

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ff149d3..6abdfe3 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,44 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * config/tc-sparc.c (v9a_asr_table): Entry for %cps removed.
+       (sparc_arch_table): Remove the HWCAP_RANDOM, HWCAP_TRANS and
+       HWCAP_ASI_CACHE_SPARING from the architectures using them.
+       (HWS_V8): New define.
+       (HWS_V9): Likewise.
+       (HWS_VA): Likewise.
+       (HWS_VB): Likewise.
+       (HWS_VC): Likewise.
+       (HWS_VD): Likewise.
+       (HWS_VE): Likewise.
+       (HWS_VV): Likewise.
+       (sparc_arch): Use the HWS_* macros.  Fix the `sparc4' architecture
+       to cover the HWCAP_ASI_BLK_INIT and HWCAP_IMA capabilities.
+       (hwcap_seen): Variable widened to 64 bits.
+       (hwcap_allowed): Likewise.
+       (sparc_arch): new field `hwcap2_allowed'.
+       (sparc_arch_table): provide hwcap2_allowed values for existing
+       archs.
+       (sparc_md_end): Add a HWCAPS2 object attribute to the elf object
+       in case any of the HWCAP2_* caps are used.
+       (sparc_ip): Take into account the new hwcaps2 bitmap to build the
+       list of seen/allowed hwcaps.
+       (get_hwcap_name): Argument widened to 64 bits to handle HWCAP2
+       bits.
+       (HWS_VM): New define.
+       (HWS2_VM): Likewise.
+       (sparc_arch): New architectures `sparc5', `v9m' and `v8plusm'.
+       (v9a_asr_table): Add the %mwait (%asr28) ancillary state register
+       to the table.
+       (sparc_ip): Handle the %mcdper ancillary state register as an
+       operand.
+       (sparc_ip): Handle } arguments as fdrd floating point registers
+       (double) that are the same than frs1.
+       * doc/c-sparc.texi (Sparc-Opts): Document the -Av9e, -Av8pluse and
+       -xarch=v9e command line options.  Also fix the description of the
+       -Av9v and -Av8plusv command line options.
+       Document the -Av9m, -Av8plusm,-Asparc5, -xarch=v9m and
+       -xarch=sparc5 command line options.
+
 2014-09-29  Terry Guo  <terry.guo@arm.com>
 
        * as.c (create_obj_attrs_section): Move it and call it from ...

diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 7497618..1d2f945 100644 (file)
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -77,11 +77,11 @@ static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
 #ifndef TE_SOLARIS
 /* Bitmask of instruction types seen so far, used to populate the
    GNU attributes section with hwcap information.  */
-static int hwcap_seen;
+static bfd_uint64_t hwcap_seen;
 #endif
 #endif
 
-static int hwcap_allowed;
+static bfd_uint64_t hwcap_allowed;
 
 static int architecture_requested;
 static int warn_on_bump;
@@ -221,6 +221,25 @@ static void output_insn (const struct sparc_opcode *, struct sparc_it *);
 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
                       v8plusa, v9, v9a, v9b, v9_64};
 
+/* Hardware capability sets, used to keep sparc_arch_table easy to
+   read.  */
+#define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
+#define HWS_V9 HWS_V8 | HWCAP_POPC
+#define HWS_VA HWS_V9 | HWCAP_VIS
+#define HWS_VB HWS_VA | HWCAP_VIS2
+#define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
+#define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
+#define HWS_VE HWS_VD                                                   \
+  | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA               \
+  | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL   \
+  | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
+#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
+#define HWS_VM HWS_VV
+
+#define HWS2_VM                                                        \
+  HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT     \
+  | HWCAP2_XMPMUL | HWCAP2_XMONT
+
 static struct sparc_arch {
   char *name;
   char *opcode_arch;
@@ -231,41 +250,50 @@ static struct sparc_arch {
   /* Allowable arg to -A?  */
   int user_option_p;
   int hwcap_allowed;
+  int hwcap2_allowed;
 } sparc_arch_table[] = {
-  { "v6", "v6", v6, 0, 1, 0 },
-  { "v7", "v7", v7, 0, 1, 0 },
-  { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
-  { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
-  { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
-  { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
-  { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
-  { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
-  { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
-  { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
-  { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
-  { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
-  { "leon", "leon", leon, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
-  { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
-  { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
-  { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
-  { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
-  { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
-  { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
-  { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
-  { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
-  { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
-  { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
-  { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
-  { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
-  { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
-  { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
-  { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
-  { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
-  { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
+  { "v6",         "v6",  v6,  0, 1, 0, 0 },
+  { "v7",         "v7",  v7,  0, 1, 0, 0 },
+  { "v8",         "v8",  v8, 32, 1, HWS_V8, 0 },
+  { "v8a",        "v8",  v8, 32, 1, HWS_V8, 0 },
+  { "sparc",      "v9",  v9,  0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
+  { "sparcvis",   "v9a", v9,  0, 1, HWS_VA, 0 },
+  { "sparcvis2",  "v9b", v9,  0, 1, HWS_VB, 0 },
+  { "sparcfmaf",  "v9b", v9,  0, 1, HWS_VB|HWCAP_FMAF, 0 },
+  { "sparcima",   "v9b", v9,  0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 },
+  { "sparcvis3",  "v9b", v9,  0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
+  { "sparcvis3r", "v9b", v9,  0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
+
+  { "sparc4",     "v9b", v9,  0, 1, HWS_VV, 0 },
+  { "sparc5",     "v9b", v9,  0, 1, HWS_VM, HWS2_VM },
+
+  { "leon",      "leon",      leon,      32, 1, HWS_V8, 0 },
+  { "sparclet",  "sparclet",  sparclet,  32, 1, HWS_V8, 0 },
+  { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 },
+  { "sparc86x",  "sparclite", sparc86x,  32, 1, HWS_V8, 0 },
+
+  { "v8plus",  "v9",  v9,  0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
+  { "v8plusa", "v9a", v9,  0, 1, HWCAP_V8PLUS|HWS_VA, 0 },
+  { "v8plusb", "v9b", v9,  0, 1, HWCAP_V8PLUS|HWS_VB, 0 },
+  { "v8plusc", "v9b", v9,  0, 1, HWCAP_V8PLUS|HWS_VC, 0 },
+  { "v8plusd", "v9b", v9,  0, 1, HWCAP_V8PLUS|HWS_VD, 0 },
+  { "v8pluse", "v9b", v9,  0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
+  { "v8plusv", "v9b", v9,  0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
+  { "v8plusm", "v9b", v9,  0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
+  
+  { "v9",      "v9",  v9,  0, 1, HWS_V9, 0 },
+  { "v9a",     "v9a", v9,  0, 1, HWS_VA, 0 },
+  { "v9b",     "v9b", v9,  0, 1, HWS_VB, 0 },
+  { "v9c",     "v9b", v9,  0, 1, HWS_VC, 0 },
+  { "v9d",     "v9b", v9,  0, 1, HWS_VD, 0 },
+  { "v9e",     "v9b", v9,  0, 1, HWS_VE, 0 },
+  { "v9v",     "v9b", v9,  0, 1, HWS_VV, 0 },
+  { "v9m",     "v9b", v9,  0, 1, HWS_VM, HWS2_VM },
+
   /* This exists to allow configure.tgt to pass one
      value to specify both the default machine and default word size.  */
-  { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
-  { NULL, NULL, v8, 0, 0, 0 }
+  { "v9-64",   "v9",  v9, 64, 0, HWS_V9, 0 },
+  { NULL, NULL, v8, 0, 0, 0, 0 }
 };
 
 /* Variant of default_arch */
@@ -516,7 +544,8 @@ md_parse_option (int c, char *arg)
        if (!architecture_requested
            || opcode_arch > max_architecture)
          max_architecture = opcode_arch;
-       hwcap_allowed |= sa->hwcap_allowed;
+       hwcap_allowed
+          |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed;
        architecture_requested = 1;
       }
       break;
@@ -810,9 +839,9 @@ struct priv_reg_entry v9a_asr_table[] =
   {"pause", 27},
   {"pic", 17},
   {"pcr", 16},
+  {"mwait", 28},
   {"gsr", 19},
   {"dcr", 18},
-  {"cps", 28},
   {"cfr", 26},
   {"clear_softint", 21},
   {"", -1},                    /* End marker.  */
@@ -942,6 +971,7 @@ void
 sparc_md_end (void)
 {
   unsigned long mach = bfd_mach_sparc;
+  int hwcaps, hwcaps2;
 
   if (sparc_arch_size == 64)
     switch (current_architecture)
@@ -965,8 +995,13 @@ sparc_md_end (void)
   bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
 
 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
-  if (hwcap_seen)
-    bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
+  hwcaps = hwcap_seen & U0xffffffff;
+  hwcaps2 = hwcap_seen >> 32;
+
+  if (hwcaps)
+    bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps);
+  if (hwcaps2)
+    bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2);
 #endif
 }
 \f
@@ -1422,7 +1457,7 @@ md_assemble (char *str)
 }
 
 static const char *
-get_hwcap_name (int mask)
+get_hwcap_name (bfd_uint64_t mask)
 {
   if (mask & HWCAP_MUL32)
     return "mul32";
@@ -1482,6 +1517,25 @@ get_hwcap_name (int mask)
     return "cbcond";
   if (mask & HWCAP_CRC32C)
     return "crc32c";
+
+  mask = mask >> 32;
+  if (mask & HWCAP2_FJATHPLUS)
+    return "fjathplus";
+  if (mask & HWCAP2_VIS3B)
+    return "vis3b";
+  if (mask & HWCAP2_ADP)
+    return "adp";
+  if (mask & HWCAP2_SPARC5)
+    return "sparc5";
+  if (mask & HWCAP2_MWAIT)
+    return "mwait";
+  if (mask & HWCAP2_XMPMUL)
+    return "xmpmul";
+  if (mask & HWCAP2_XMONT)
+    return "xmont";
+  if (mask & HWCAP2_NSEC)
+    return "nsec";
+
   return "UNKNOWN";
 }
 
@@ -2306,6 +2360,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
            case 'g':
            case 'H':
            case 'J':
+           case '}':
              {
                char format;
 
@@ -2368,6 +2423,13 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
                    break;
                  }     /* if not an 'f' register.  */
 
+               if (*args == '}' && mask != RS2 (opcode))
+                 {
+                   error_message
+                     = _(": Instruction requires frs2 and frsd must be the same register");
+                   goto error;
+                 }
+
                switch (*args)
                  {
                  case 'v':
@@ -2390,6 +2452,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
                  case 'g':
                  case 'H':
                  case 'J':
+                 case '}':
                    opcode |= RD (mask);
                    continue;
                  }             /* Pack it in.  */
@@ -2843,6 +2906,12 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
              s += 5;
              continue;
 
+           case '{':
+             if (strncmp (s, "%mcdper",7) != 0)
+               break;
+             s += 7;
+             continue;
+
            case 'E':
              if (strncmp (s, "%ccr", 4) != 0)
                break;
@@ -2933,7 +3002,8 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
        {
          /* We have a match.  Now see if the architecture is OK.  */
          int needed_arch_mask = insn->architecture;
-         int hwcaps = insn->hwcaps;
+         bfd_uint64_t hwcaps
+           = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps;
 
 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
          if (hwcaps)

diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi
index 8915528..6036766 100644 (file)
--- a/gas/doc/c-sparc.texi
+++ b/gas/doc/c-sparc.texi
@@ -60,7 +60,9 @@ is explicitly requested.  SPARC v9 is always incompatible with sparclite.
 @kindex -Av9b
 @kindex -Av9c
 @kindex -Av9d
+@kindex -Av9e
 @kindex -Av9v
+@kindex -Av9m
 @kindex -Asparc
 @kindex -Asparcvis
 @kindex -Asparcvis2
@@ -70,7 +72,7 @@ is explicitly requested.  SPARC v9 is always incompatible with sparclite.
 @kindex -Asparcvis3r
 @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
 @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
-@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
+@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m
 @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
 @itemx -Asparcvis3 | -Asparcvis3r
 Use one of the @samp{-A} options to select one of the SPARC
@@ -81,9 +83,10 @@ or feature requiring an incompatible or higher level.
 @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
 @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
 
-@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
-@samp{-Av9v} select a 64 bit environment and are not available unless GAS
-is explicitly configured with 64 bit environment support.
+@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d},
+@samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit
+environment and are not available unless GAS is explicitly configured
+with 64 bit environment support.
 
 @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
 UltraSPARC VIS 1.0 extensions.
@@ -98,10 +101,17 @@ as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
 multiply-add, VIS 3.0, and HPC extension instructions, as well as the
 instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
 
-@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
-memory, floating point unfused multiply-add, integer multiply-add, and
-cache sparing store instructions, as well as the instructions enabled
-by @samp{-Av8plusd} and @samp{-Av9d}.
+@samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic
+instructions, as well as the instructions enabled by @samp{-Av8plusd}
+and @samp{-Av9d}.
+
+@samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused
+multiply-add, and integer multiply-add, as well as the instructions
+enabled by @samp{-Av8pluse} and @samp{-Av9e}.
+
+@samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended,
+xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
+enabled by @samp{-Av8plusv} and @samp{-Av9v}.
 
 @samp{-Asparc} specifies a v9 environment.  It is equivalent to
 @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
@@ -121,21 +131,22 @@ multiply-add instructions enabled.
 @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
 HPC , and floating point fused multiply-add instructions enabled.
 
-@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
-HPC, transactional memory, random, and floating point unfused multiply-add
-instructions enabled.
+@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC,
+and floating point unfused multiply-add instructions enabled.
+
+@samp{-Asparc5} is equivalent to @samp{-Av9m}.
 
 @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
 @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
-@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
+@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m
 @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
-@itemx -xarch=sparcvis3r
+@itemx -xarch=sparcvis3r | -xarch=sparc5
 For compatibility with the SunOS v9 assembler.  These options are
 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
--Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
--Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
-respectively.
+-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
+-Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
+-Asparcvis3, and -Asparcvis3r, respectively.
 
 @item -bump
 Warn whenever it is necessary to switch to another level.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5d74cea..68aa318 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * gas/sparc/hpcvis3.d: Remove tests for the `chkpt', `commit',
+       `random', `wr r,i,%cps' and `rd r,%cps' instructions.
+       * gas/sparc/hpcvis3.s: Likewise.
+       * gas/sparc/xcrypto.d: New file.
+       * gas/sparc/xcrypto.s: Likewise.
+       * gas/sparc/mwait.d: New file.
+       * gas/sparc/mwait.s: Likewise.
+       * gas/sparc/mcdper.s: New file.
+       * gas/sparc/mcdper.d: Likewise.
+       * gas/sparc/sparc5vis4.d: New file.
+       * gas/sparc/sparc5vis4.s: Likewise.
+       * gas/sparc/sparc.exp (sparc_elf_setup): Run the xcrypto test.
+       Run the mwait test.
+       Run the mcdper test.
+`      Run the sparc5vis4 test.
+
 2014-09-27  Alan Modra  <amodra@gmail.com>
 
        * gas/elf/group2.d, * gas/elf/group2.s: New test.

diff --git a/gas/testsuite/gas/sparc/hpcvis3.d b/gas/testsuite/gas/sparc/hpcvis3.d
index 8b920a5..2c09504 100644 (file)
--- a/gas/testsuite/gas/sparc/hpcvis3.d
+++ b/gas/testsuite/gas/sparc/hpcvis3.d
@@ -7,11 +7,11 @@
 Disassembly of section .text:
 
 0+ <.text>:
-   0:  83 47 00 00     rd  %cps, %g1
-   4:  b9 80 a0 03     wr  %g2, 3, %cps
+   0:  01 00 00 00     nop 
+   4:  01 00 00 00     nop 
    8:  c7 08 c0 00     ldx  \[ %g3 \], %efsr
-   c:  30 50 00 01     chkpt  0x10
-  10:  bd f0 00 00     commit 
+   c:  01 00 00 00     nop 
+  10:  01 00 00 00     nop 
   14:  87 a0 4a 22     fnadds  %f1, %f2, %f3
   18:  8d a0 8a 44     fnaddd  %f2, %f4, %f6
   1c:  8f a0 cb 25     fnmuls  %f3, %f5, %f7
@@ -41,7 +41,7 @@ Disassembly of section .text:
   7c:  95 f9 11 c6     fnumaddd  %f4, %f6, %f8, %f10
   80:  8f b1 42 26     addxc  %g5, %g6, %g7
   84:  97 b2 42 6a     addxccc  %o1, %o2, %o3
-  88:  8d b0 02 a0     random  %f6
+  88:  01 00 00 00     nop 
   8c:  9f b3 42 ce     umulxhi  %o5, %sp, %o7
   90:  b5 b0 02 f9     lzcnt  %i1, %i2
   94:  81 b0 03 7b     cmask8  %i3

diff --git a/gas/testsuite/gas/sparc/hpcvis3.s b/gas/testsuite/gas/sparc/hpcvis3.s
index e960557..0fe151c 100644 (file)
--- a/gas/testsuite/gas/sparc/hpcvis3.s
+++ b/gas/testsuite/gas/sparc/hpcvis3.s
@@ -1,10 +1,10 @@
 # Test HPC/VIS3 instructions
        .text
-       rd      %cps, %g1
-       wr      %g2, 0x3, %cps
+       nop 
+       nop 
        ldx     [%g3], %efsr
-       chkpt   1f
-1:     commit
+       nop
+1:     nop
        fnadds  %f1, %f2, %f3
        fnaddd  %f2, %f4, %f6
        fnmuls  %f3, %f5, %f7
@@ -34,7 +34,7 @@
        fnumaddd %f4, %f6, %f8, %f10
        addxc   %g5, %g6, %g7
        addxccc %o1, %o2, %o3
-       random  %f6
+       nop
        umulxhi %o5, %o6, %o7
        lzcnt   %i1, %i2
        cmask8  %i3

diff --git a/gas/testsuite/gas/sparc/mcdper.d b/gas/testsuite/gas/sparc/mcdper.d
new file mode 100644 (file)
index 0000000..f37f4b3
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mcdper.d
@@ -0,0 +1,15 @@
+#as: -Av9m
+#objdump: -dr
+#name: sparc OSA2015 %mcdper asr
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  83 43 80 00     rd  %mcdper, %g1
+   4:  9d 80 60 03     wr  %g1, 3, %mcdper
+   8:  9d 80 40 02     wr  %g1, %g2, %mcdper
+
+
+

diff --git a/gas/testsuite/gas/sparc/mcdper.s b/gas/testsuite/gas/sparc/mcdper.s
new file mode 100644 (file)
index 0000000..0891424
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mcdper.s
@@ -0,0 +1,5 @@
+# Test reads/writes to the %mcdper asr register
+       .text
+       rd      %mcdper, %g1
+       wr      %g1, 0x3, %mcdper
+       wr      %g1, %g2, %mcdper

diff --git a/gas/testsuite/gas/sparc/mwait.d b/gas/testsuite/gas/sparc/mwait.d
new file mode 100644 (file)
index 0000000..bbae4fd
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mwait.d
@@ -0,0 +1,13 @@
+#as: -Av9m
+#objdump: -dr
+#name: sparc OSA2015 %mwait asr and MWAIT instruction
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  83 47 00 00     rd  %mwait, %g1
+   4:  b9 80 a0 03     wr  %g2, 3, %mwait
+   8:  b9 80 00 01     mwait  %g1
+   c:  b9 80 20 03     mwait  3

diff --git a/gas/testsuite/gas/sparc/mwait.s b/gas/testsuite/gas/sparc/mwait.s
new file mode 100644 (file)
index 0000000..0379746
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mwait.s
@@ -0,0 +1,7 @@
+# Test reads/writes to the %mwait asr register and the MWAIT
+# instruction
+       .text
+       rd      %mwait, %g1
+       wr      %g2, 0x3, %mwait
+       mwait   %g1
+       mwait   0x3

diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index 0504b8f..8178e0c 100644 (file)
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -79,6 +79,7 @@ if [istarget sparc*-*-*] {
     run_dump_test "hpcvis3"
     run_dump_test "ima"
     run_dump_test "crypto"
+    run_dump_test "xcrypto"
     run_dump_test "cbcond"
     run_dump_test "pause"
     run_dump_test "cfr"
@@ -89,6 +90,9 @@ if [istarget sparc*-*-*] {
     run_dump_test "ld_st_fsr"
     run_dump_test "edge"
     run_dump_test "flush"
+    run_dump_test "mwait"
+    run_dump_test "mcdper"
+    run_dump_test "sparc5vis4"
 
     run_list_test "pr4587" ""
 }

diff --git a/gas/testsuite/gas/sparc/sparc5vis4.d b/gas/testsuite/gas/sparc/sparc5vis4.d
new file mode 100644 (file)
index 0000000..61a2de8
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc5vis4.d
@@ -0,0 +1,38 @@
+#as: -Av9m
+#objdump: -dr
+#name: sparc SPARC5 and VIS4.0
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  87 b0 48 22     subxc  %g1, %g2, %g3
+   4:  87 b0 48 62     subxccc  %g1, %g2, %g3
+   8:  91 b0 a4 84     fpadd8  %f2, %f4, %f8
+   c:  99 b2 24 ca     fpadds8  %f8, %f10, %f12
+  10:  a1 b3 24 ee     fpaddus8  %f12, %f14, %f16
+  14:  a9 b4 24 72     fpaddus16  %f16, %f18, %f20
+  18:  83 b0 86 84     fpcmple8  %f2, %f4, %g1
+  1c:  85 b1 07 86     fpcmpgt8  %f4, %f6, %g2
+  20:  87 b1 a5 c8     fpcmpule16  %f6, %f8, %g3
+  24:  89 b2 25 6a     fpcmpugt16  %f8, %f10, %g4
+  28:  8b b2 a5 ec     fpcmpule32  %f10, %f12, %g5
+  2c:  8d b3 25 8e     fpcmpugt32  %f12, %f14, %g6
+  30:  a5 b3 a3 b0     fpmax8  %f14, %f16, %f18
+  34:  ad b4 a3 d4     fpmax16  %f18, %f20, %f22
+  38:  b5 b5 a3 f8     fpmax32  %f22, %f24, %f26
+  3c:  bd b6 ab bc     fpmaxu8  %f26, %f28, %f30
+  40:  87 b7 ab c1     fpmaxu16  %f30, %f32, %f34
+  44:  8f b0 eb e5     fpmaxu32  %f34, %f36, %f38
+  48:  97 b1 e3 49     fpmin8  %f38, %f40, %f42
+  4c:  9f b2 e3 6d     fpmin16  %f42, %f44, %f46
+  50:  a7 b3 e3 91     fpmin32  %f46, %f48, %f50
+  54:  af b4 eb 55     fpminu8  %f50, %f52, %f54
+  58:  b7 b5 eb 79     fpminu16  %f54, %f56, %f58
+  5c:  bf b6 eb 9d     fpminu32  %f58, %f60, %f62
+  60:  8d b0 aa 84     fpsub8  %f2, %f4, %f6
+  64:  95 b1 aa c8     fpsubs8  %f6, %f8, %f10
+  68:  9d b2 aa ec     fpsubus8  %f10, %f12, %f14
+  6c:  a5 b3 aa 70     fpsubus16  %f14, %f16, %f18
+  70:  bf b0 09 3f     faligndatai  %f0, %f62, %f4, %f62

diff --git a/gas/testsuite/gas/sparc/sparc5vis4.s b/gas/testsuite/gas/sparc/sparc5vis4.s
new file mode 100644 (file)
index 0000000..4bd7942
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc5vis4.s
@@ -0,0 +1,31 @@
+# Test SPARC5/VIS4 instructions
+       .text
+       subxc   %g1, %g2, %g3
+       subxccc %g1, %g2, %g3
+       fpadd8  %f2, %f4, %f8
+       fpadds8 %f8, %f10, %f12
+       fpaddus8 %f12, %f14, %f16
+       fpaddus16 %f16, %f18, %f20
+       fpcmple8 %f2, %f4, %g1
+       fpcmpgt8 %f4, %f6, %g2
+       fpcmpule16 %f6, %f8, %g3
+       fpcmpugt16 %f8, %f10, %g4
+       fpcmpule32 %f10, %f12, %g5
+       fpcmpugt32 %f12, %f14, %g6
+       fpmax8  %f14, %f16, %f18
+       fpmax16 %f18, %f20, %f22
+       fpmax32 %f22, %f24, %f26
+       fpmaxu8 %f26, %f28, %f30
+       fpmaxu16 %f30, %f32, %f34
+       fpmaxu32 %f34, %f36, %f38
+       fpmin8  %f38, %f40, %f42
+       fpmin16 %f42, %f44, %f46
+       fpmin32 %f46, %f48, %f50
+       fpminu8 %f50, %f52, %f54
+       fpminu16 %f54, %f56, %f58
+       fpminu32 %f58, %f60, %f62
+       fpsub8  %f2, %f4, %f6
+       fpsubs8 %f6, %f8, %f10
+       fpsubus8 %f10, %f12, %f14
+       fpsubus16 %f14, %f16, %f18
+       faligndatai %f0, %f62, %f4, %f62

diff --git a/gas/testsuite/gas/sparc/xcrypto.d b/gas/testsuite/gas/sparc/xcrypto.d
new file mode 100644 (file)
index 0000000..fbf8ba3
--- /dev/null
+++ b/gas/testsuite/gas/sparc/xcrypto.d
@@ -0,0 +1,105 @@
+#as: -Av9m
+#objdump: -dr
+#name: OSA2015 crypto instructions
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:  83 b0 29 00     xmpmul  0
+   4:  83 b0 29 01     xmpmul  1
+   8:  83 b0 29 02     xmpmul  2
+   c:  83 b0 29 03     xmpmul  3
+  10:  83 b0 29 04     xmpmul  4
+  14:  83 b0 29 05     xmpmul  5
+  18:  83 b0 29 06     xmpmul  6
+  1c:  83 b0 29 07     xmpmul  7
+  20:  83 b0 29 08     xmpmul  8
+  24:  83 b0 29 09     xmpmul  9
+  28:  83 b0 29 0a     xmpmul  0xa
+  2c:  83 b0 29 0b     xmpmul  0xb
+  30:  83 b0 29 0c     xmpmul  0xc
+  34:  83 b0 29 0d     xmpmul  0xd
+  38:  83 b0 29 0e     xmpmul  0xe
+  3c:  83 b0 29 0f     xmpmul  0xf
+  40:  83 b0 29 10     xmpmul  0x10
+  44:  83 b0 29 11     xmpmul  0x11
+  48:  83 b0 29 12     xmpmul  0x12
+  4c:  83 b0 29 13     xmpmul  0x13
+  50:  83 b0 29 14     xmpmul  0x14
+  54:  83 b0 29 15     xmpmul  0x15
+  58:  83 b0 29 16     xmpmul  0x16
+  5c:  83 b0 29 17     xmpmul  0x17
+  60:  83 b0 29 18     xmpmul  0x18
+  64:  83 b0 29 19     xmpmul  0x19
+  68:  83 b0 29 1a     xmpmul  0x1a
+  6c:  83 b0 29 1b     xmpmul  0x1b
+  70:  83 b0 29 1c     xmpmul  0x1c
+  74:  83 b0 29 1d     xmpmul  0x1d
+  78:  83 b0 29 1e     xmpmul  0x1e
+  7c:  83 b0 29 1f     xmpmul  0x1f
+  80:  83 b0 29 20     xmontmul  0
+  84:  83 b0 29 21     xmontmul  1
+  88:  83 b0 29 22     xmontmul  2
+  8c:  83 b0 29 23     xmontmul  3
+  90:  83 b0 29 24     xmontmul  4
+  94:  83 b0 29 25     xmontmul  5
+  98:  83 b0 29 26     xmontmul  6
+  9c:  83 b0 29 27     xmontmul  7
+  a0:  83 b0 29 28     xmontmul  8
+  a4:  83 b0 29 29     xmontmul  9
+  a8:  83 b0 29 2a     xmontmul  0xa
+  ac:  83 b0 29 2b     xmontmul  0xb
+  b0:  83 b0 29 2c     xmontmul  0xc
+  b4:  83 b0 29 2d     xmontmul  0xd
+  b8:  83 b0 29 2e     xmontmul  0xe
+  bc:  83 b0 29 2f     xmontmul  0xf
+  c0:  83 b0 29 30     xmontmul  0x10
+  c4:  83 b0 29 31     xmontmul  0x11
+  c8:  83 b0 29 32     xmontmul  0x12
+  cc:  83 b0 29 33     xmontmul  0x13
+  d0:  83 b0 29 34     xmontmul  0x14
+  d4:  83 b0 29 35     xmontmul  0x15
+  d8:  83 b0 29 36     xmontmul  0x16
+  dc:  83 b0 29 37     xmontmul  0x17
+  e0:  83 b0 29 38     xmontmul  0x18
+  e4:  83 b0 29 39     xmontmul  0x19
+  e8:  83 b0 29 3a     xmontmul  0x1a
+  ec:  83 b0 29 3b     xmontmul  0x1b
+  f0:  83 b0 29 3c     xmontmul  0x1c
+  f4:  83 b0 29 3d     xmontmul  0x1d
+  f8:  83 b0 29 3e     xmontmul  0x1e
+  fc:  83 b0 29 3f     xmontmul  0x1f
+ 100:  83 b0 29 40     xmontsqr  0
+ 104:  83 b0 29 41     xmontsqr  1
+ 108:  83 b0 29 42     xmontsqr  2
+ 10c:  83 b0 29 43     xmontsqr  3
+ 110:  83 b0 29 44     xmontsqr  4
+ 114:  83 b0 29 45     xmontsqr  5
+ 118:  83 b0 29 46     xmontsqr  6
+ 11c:  83 b0 29 47     xmontsqr  7
+ 120:  83 b0 29 48     xmontsqr  8
+ 124:  83 b0 29 49     xmontsqr  9
+ 128:  83 b0 29 4a     xmontsqr  0xa
+ 12c:  83 b0 29 4b     xmontsqr  0xb
+ 130:  83 b0 29 4c     xmontsqr  0xc
+ 134:  83 b0 29 4d     xmontsqr  0xd
+ 138:  83 b0 29 4e     xmontsqr  0xe
+ 13c:  83 b0 29 4f     xmontsqr  0xf
+ 140:  83 b0 29 50     xmontsqr  0x10
+ 144:  83 b0 29 51     xmontsqr  0x11
+ 148:  83 b0 29 52     xmontsqr  0x12
+ 14c:  83 b0 29 53     xmontsqr  0x13
+ 150:  83 b0 29 54     xmontsqr  0x14
+ 154:  83 b0 29 55     xmontsqr  0x15
+ 158:  83 b0 29 56     xmontsqr  0x16
+ 15c:  83 b0 29 57     xmontsqr  0x17
+ 160:  83 b0 29 58     xmontsqr  0x18
+ 164:  83 b0 29 59     xmontsqr  0x19
+ 168:  83 b0 29 5a     xmontsqr  0x1a
+ 16c:  83 b0 29 5b     xmontsqr  0x1b
+ 170:  83 b0 29 5c     xmontsqr  0x1c
+ 174:  83 b0 29 5d     xmontsqr  0x1d
+ 178:  83 b0 29 5e     xmontsqr  0x1e
+ 17c:  83 b0 29 5f     xmontsqr  0x1f

diff --git a/gas/testsuite/gas/sparc/xcrypto.s b/gas/testsuite/gas/sparc/xcrypto.s
new file mode 100644 (file)
index 0000000..d793ce0
--- /dev/null
+++ b/gas/testsuite/gas/sparc/xcrypto.s
@@ -0,0 +1,98 @@
+# Test OSA2015 CRYPTO instructions
+       .text
+       xmpmul  0
+       xmpmul  1
+       xmpmul  2
+       xmpmul  3
+       xmpmul  4
+       xmpmul  5
+       xmpmul  6
+       xmpmul  7
+       xmpmul  8
+       xmpmul  9
+       xmpmul  10
+       xmpmul  11
+       xmpmul  12
+       xmpmul  13
+       xmpmul  14
+       xmpmul  15
+       xmpmul  16
+       xmpmul  17
+       xmpmul  18
+       xmpmul  19
+       xmpmul  20
+       xmpmul  21
+       xmpmul  22
+       xmpmul  23
+       xmpmul  24
+       xmpmul  25
+       xmpmul  26
+       xmpmul  27
+       xmpmul  28
+       xmpmul  29
+       xmpmul  30
+       xmpmul  31
+       xmontmul        0
+       xmontmul        1
+       xmontmul        2
+       xmontmul        3
+       xmontmul        4
+       xmontmul        5
+       xmontmul        6
+       xmontmul        7
+       xmontmul        8
+       xmontmul        9
+       xmontmul        10
+       xmontmul        11
+       xmontmul        12
+       xmontmul        13
+       xmontmul        14
+       xmontmul        15
+       xmontmul        16
+       xmontmul        17
+       xmontmul        18
+       xmontmul        19
+       xmontmul        20
+       xmontmul        21
+       xmontmul        22
+       xmontmul        23
+       xmontmul        24
+       xmontmul        25
+       xmontmul        26
+       xmontmul        27
+       xmontmul        28
+       xmontmul        29
+       xmontmul        30
+       xmontmul        31
+       xmontsqr        0
+       xmontsqr        1
+       xmontsqr        2
+       xmontsqr        3
+       xmontsqr        4
+       xmontsqr        5
+       xmontsqr        6
+       xmontsqr        7
+       xmontsqr        8
+       xmontsqr        9
+       xmontsqr        10
+       xmontsqr        11
+       xmontsqr        12
+       xmontsqr        13
+       xmontsqr        14
+       xmontsqr        15
+       xmontsqr        16
+       xmontsqr        17
+       xmontsqr        18
+       xmontsqr        19
+       xmontsqr        20
+       xmontsqr        21
+       xmontsqr        22
+       xmontsqr        23
+       xmontsqr        24
+       xmontsqr        25
+       xmontsqr        26
+       xmontsqr        27
+       xmontsqr        28
+       xmontsqr        29
+       xmontsqr        30
+       xmontsqr        31

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 7e92493..17978ba 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,18 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc.h (Tag_GNU_Sparc_HWCAPS2): New object attribute.
+       (ELF_SPARC_HWCAP2_FJATHPLUS): New HWCAP2 bitmask value.
+       (ELF_SPARC_HWCAP2_VIS3B): Likewise.
+       (ELF_SPARC_HWCAP2_ADP): Likewise.
+       (ELF_SPARC_HWCAP2_SPARC5): Likewise.
+       (ELF_SPARC_HWCAP2_MWAIT): Likewise.
+       (ELF_SPARC_HWCAP2_XMPMUL): Likewise.
+       (ELF_SPARC_HWCAP2_XMONT): Likewise.
+       (ELF_SPARC_HWCAP2_NSEC): Likewise.
+       (ELF_SPARC_HWCAP2_FJATHHPC): Likewise.
+       (ELF_SPARC_HWCAP2_FJDES): Likewise.
+       (ELF_SPARC_HWCAP2_FJAES): Likewise.
+
 2014-10-08  Will Newton  <will.newton@linaro.org>
 
        * aarch64.h: Sync up relocations with ABI release 1.0.

diff --git a/include/elf/sparc.h b/include/elf/sparc.h
index 9bfc27f..d41ba35 100644 (file)
--- a/include/elf/sparc.h
+++ b/include/elf/sparc.h
@@ -190,9 +190,19 @@ enum
 {
   /* 0-3 are generic.  */
   Tag_GNU_Sparc_HWCAPS = 4,
+  Tag_GNU_Sparc_HWCAPS2 = 8
 };
 
-/* These values match the AV_SPARC_* hwcap bits defined under Solaris.  */
+/* Generally speaking the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
+   values match the AV_SPARC_* and AV2_SPARC_* bits respectively.
+
+   However Solaris 11 introduced a backwards-incompatible change
+   deprecating the RANDOM, TRANS and ASI_CACHE_SPARING bits in the
+   AT_SUNW_CAP_HW1 flags, reusing the bits for the unrelated hwcaps
+   FJATHHPC, FJDES and FJAES respectively.  In GNU/Linux we opted to
+   keep the old hwcaps in Tag_GNU_Sparc_HWCAPS and allocate bits for
+   FJATHHPC, FJDES and JFAES in Tag_GNU_Sparc_HWCAPS2.  */
+
 #define ELF_SPARC_HWCAP_MUL32  0x00000001 /* umul/umulcc/smul/smulcc insns */
 #define ELF_SPARC_HWCAP_DIV32  0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
 #define ELF_SPARC_HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
@@ -226,4 +236,17 @@ enum
 #define ELF_SPARC_HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
 #define ELF_SPARC_HWCAP_CRC32C 0x20000000 /* CRC32C insn */
 
+#define ELF_SPARC_HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
+#define ELF_SPARC_HWCAP2_VIS3B     0x00000002 /* VIS3 present on multiple chips */
+#define ELF_SPARC_HWCAP2_ADP       0x00000004 /* Application Data Protection */
+#define ELF_SPARC_HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
+#define ELF_SPARC_HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
+#define ELF_SPARC_HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
+#define ELF_SPARC_HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
+#define ELF_SPARC_HWCAP2_NSEC      \
+                                   0x00000080 /* pause insn with support for nsec timings */
+#define ELF_SPARC_HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
+#define ELF_SPARC_HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
+#define ELF_SPARC_HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
+
 #endif /* _ELF_SPARC_H */

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index e16393f..d378910 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,23 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc.h (sparc_opcode): new field `hwcaps2'.
+       (HWCAP2_FJATHPLUS): New define.
+       (HWCAP2_VIS3B): Likewise.
+       (HWCAP2_ADP): Likewise.
+       (HWCAP2_SPARC5): Likewise.
+       (HWCAP2_MWAIT): Likewise.
+       (HWCAP2_XMPMUL): Likewise.
+       (HWCAP2_XMONT): Likewise.
+       (HWCAP2_NSEC): Likewise.
+       (HWCAP2_FJATHHPC): Likewise.
+       (HWCAP2_FJDES): Likewise.
+       (HWCAP2_FJAES): Likewise.
+       Document the new operand kind `{', corresponding to the mcdper
+       ancillary state register.
+       Document the new operand kind }, which represents frsd floating
+       point registers (double precision) which must be the same than
+       frs1 in its containing instruction.
+
 2014-09-16  Kuan-Lin Chen <kuanlinchentw@gmail.com>
 
         * nds32.h: Add new opcode declaration.

diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index b80876a..cf4ff1c 100644 (file)
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -100,6 +100,7 @@ typedef struct sparc_opcode
   /* This was called "delayed" in versions before the flags.  */
   unsigned int flags;
   unsigned int hwcaps;
+  unsigned int hwcaps2;
   short architecture;  /* Bitmask of sparc_opcode_arch_val's.  */
 } sparc_opcode;
 
@@ -115,7 +116,8 @@ typedef struct sparc_opcode
 
 #define F_PREF_ALIAS   (F_ALIAS|F_PREFERRED)
 
-/* These must match the HWCAP_* values precisely.  */
+/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
+   values precisely.  See include/elf/sparc.h.  */
 #define HWCAP_MUL32    0x00000001 /* umul/umulcc/smul/smulcc insns */
 #define HWCAP_DIV32    0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
 #define HWCAP_FSMULD   0x00000004 /* 'fsmuld' insn */
@@ -148,6 +150,20 @@ typedef struct sparc_opcode
 #define HWCAP_CBCOND   0x10000000 /* Compare and Branch insns */
 #define HWCAP_CRC32C   0x20000000 /* CRC32C insn */
 
+#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
+#define HWCAP2_VIS3B     0x00000002 /* VIS3 present on multiple chips */
+#define HWCAP2_ADP       0x00000004 /* Application Data Protection */
+#define HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
+#define HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
+#define HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
+#define HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
+#define HWCAP2_NSEC      \
+                         0x00000080 /* pause insn with support for nsec timings */
+#define HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
+#define HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
+#define HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
+
+
 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
    macro), which is 64 bits. It is handled as a special case.
 
@@ -173,6 +189,7 @@ typedef struct sparc_opcode
        g       frsd floating point register.
        H       frsd floating point register (double/even).
        J       frsd floating point register (quad/multiple of 4).
+       }       frsd floating point register (double/even) that is == frs2
        b       crs1 coprocessor register
        c       crs2 coprocessor register
        D       crsd coprocessor register
@@ -214,6 +231,7 @@ typedef struct sparc_opcode
        s       %fprs. (v9)
        P       %pc.  (v9)
        W       %tick.  (v9)
+       {       %mcdper. (v9b)
        o       %asi. (v9)
        6       %fcc0. (v9)
        7       %fcc1. (v9)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e5bcb13..b02424d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,24 @@
+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
+       `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
+       Annotate table with HWCAP2 bits.
+       Add instructions xmontmul, xmontsqr, xmpmul.
+       (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
+       r,i,%mwait' and `rd %mwait,r' instructions.
+       Add rd/wr instructions for accessing the %mcdper ancillary state
+       register.
+       (sparc-opcodes): Add sparc5/vis4.0 instructions:
+       subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
+       fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
+       fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
+       fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
+       fpsubus16, and faligndatai.
+       * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
+       ancillary state register to the table.
+       (print_insn_sparc): Handle the %mcdper ancillary state register.
+       (print_insn_sparc): Handle new operand type '}'.
+
 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (MOD_0F20): Removed.

diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index db09c44..9f0b96e 100644 (file)
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -106,7 +106,7 @@ static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
   "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
-  "pause", "cps"
+  "pause", "mwait"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
@@ -656,6 +656,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    break;
                  case 'H':     /* Double/even.  */
                  case 'J':     /* Quad/multiple of 4.  */
+                 case '}':     /* Double/even.  */
                    fregx (X_RD (insn));
                    break;
 #undef freg
@@ -793,6 +794,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
                    (*info->fprintf_func) (stream, "%%fprs");
                    break;
 
+                 case '{':
+                   (*info->fprintf_func) (stream, "%%mcdper");
+                   break;
+
                  case 'o':
                    (*info->fprintf_func) (stream, "%%asi");
                    break;

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 67176e6..1150b2f 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -176,949 +176,951 @@ sparc_opcode_lookup_arch (const char *name)
 /* Entries for commutative arithmetic operations.  */
 /* ??? More entries can make use of this.  */
 #define COMMUTEOP(opcode, op3, arch_mask) \
-{ opcode,      F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),        "1,2,d", 0, 0, arch_mask }, \
-{ opcode,      F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, 0, arch_mask }, \
-{ opcode,      F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, 0, arch_mask }
+{ opcode,      F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),        "1,2,d", 0, 0, 0, arch_mask }, \
+{ opcode,      F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, 0, 0, arch_mask }, \
+{ opcode,      F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, 0, 0, arch_mask }
 
 const struct sparc_opcode sparc_opcodes[] = {
 
-{ "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", 0, 0, v6 },
-{ "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", 0, 0, v6 }, /* ld [rs1+%g0],d */
-{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, 0, v6 },
-{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, 0, v6 },
-{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* ld [rs1+0],d */
-{ "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0),              "[1+2],g", 0, 0, v6 },
-{ "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,       "[1],g", 0, 0, v6 }, /* ld [rs1+%g0],d */
-{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, 0, v6 },
-{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, 0, v6 },
-{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, 0, v6 },
-{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),   "[1],g", 0, 0, v6 }, /* ld [rs1+0],d */
-
-{ "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),       "[1+2],F", 0, 0, v6 },
-{ "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+%g0],d */
-{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[1+i],F", 0, 0, v6 },
-{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[i+1],F", 0, 0, v6 },
-{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, v6 },
-{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+0],d */
-
-{ "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2],D", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1],D", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
-{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i],D", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1],D", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i],D", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1],D", 0, 0, v6notv9 }, /* ld [rs1+0],d */
-{ "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0),              "[1+2],C", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,       "[1],C", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
-{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[1+i],C", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[i+1],C", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,       "[i],C", 0, 0, v6notv9 },
-{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),   "[1],C", 0, 0, v6notv9 }, /* ld [rs1+0],d */
+{ "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v6 }, /* ld [rs1+0],d */
+{ "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0),              "[1+2],g", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,       "[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),   "[1],g", 0, 0, 0, v6 }, /* ld [rs1+0],d */
+
+{ "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),       "[1+2],F", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */
+{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[1+i],F", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[i+1],F", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, 0, v6 },
+{ "ld",        F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+0],d */
+
+{ "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2],D", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
+{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i],D", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1],D", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i],D", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */
+{ "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0),              "[1+2],C", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,       "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
+{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[1+i],C", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[i+1],C", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,       "[i],C", 0, 0, 0, v6notv9 },
+{ "ld",        F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),   "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */
 
 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
    'ld' pseudo-op in v9.  */
-{ "lduw",      F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", F_ALIAS, 0, v9 },
-{ "lduw",      F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+%g0],d */
-{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", F_ALIAS, 0, v9 },
-{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", F_ALIAS, 0, v9 },
-{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", F_ALIAS, 0, v9 },
-{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldtw",      F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, 0, v9 },
-{ "ldtw",      F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v9 }, /* ldd [rs1+%g0],d */
-{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, 0, v9 },
-{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, 0, v9 },
-{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, 0, v9 },
-{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, 0, v9 }, /* ldd [rs1+0],d */
-
-{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", F_ALIAS, 0, v6 }, /* ldd [rs1+%g0],d */
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, 0, v6 }, /* ldd [rs1+0],d */
-{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", F_ALIAS, 0, v6 }, /* ldd [rs1+%g0],d */
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", F_ALIAS, 0, v6 },
-{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", F_ALIAS, 0, v6 }, /* ldd [rs1+0],d */
-
-{ "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),      "[1+2],D", 0, 0, v6notv9 },
-{ "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */
-{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i],D", 0, 0, v6notv9 },
-{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1],D", 0, 0, v6notv9 },
-{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i],D", 0, 0, v6notv9 },
-{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+0],d */
-
-{ "ldq",       F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),      "[1+2],J", 0, 0, v9 },
-{ "ldq",       F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),  "[1],J", 0, 0, v9 }, /* ldd [rs1+%g0],d */
-{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[1+i],J", 0, 0, v9 },
-{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[i+1],J", 0, 0, v9 },
-{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,       "[i],J", 0, 0, v9 },
-{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),   "[1],J", 0, 0, v9 }, /* ldd [rs1+0],d */
-
-{ "ldsb",      F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),      "[1+2],d", 0, 0, v6 },
-{ "ldsb",      F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v6 }, /* ldsb [rs1+%g0],d */
-{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[1+i],d", 0, 0, v6 },
-{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[i+1],d", 0, 0, v6 },
-{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* ldsb [rs1+0],d */
-
-{ "ldsh",      F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v6 }, /* ldsh [rs1+%g0],d */
-{ "ldsh",      F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),      "[1+2],d", 0, 0, v6 },
-{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[1+i],d", 0, 0, v6 },
-{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[i+1],d", 0, 0, v6 },
-{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* ldsh [rs1+0],d */
-
-{ "ldstub",    F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),      "[1+2],d", 0, 0, v6 },
-{ "ldstub",    F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v6 }, /* ldstub [rs1+%g0],d */
-{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[1+i],d", 0, 0, v6 },
-{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[i+1],d", 0, 0, v6 },
-{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* ldstub [rs1+0],d */
-
-{ "ldsw",      F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),      "[1+2],d", 0, 0, v9 },
-{ "ldsw",      F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v9 }, /* ldsw [rs1+%g0],d */
-{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[1+i],d", 0, 0, v9 },
-{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[i+1],d", 0, 0, v9 },
-{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,       "[i],d", 0, 0, v9 },
-{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),   "[1],d", 0, 0, v9 }, /* ldsw [rs1+0],d */
-
-{ "ldub",      F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),      "[1+2],d", 0, 0, v6 },
-{ "ldub",      F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v6 }, /* ldub [rs1+%g0],d */
-{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[1+i],d", 0, 0, v6 },
-{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[i+1],d", 0, 0, v6 },
-{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* ldub [rs1+0],d */
-
-{ "lduh",      F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),      "[1+2],d", 0, 0, v6 },
-{ "lduh",      F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v6 }, /* lduh [rs1+%g0],d */
-{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[1+i],d", 0, 0, v6 },
-{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[i+1],d", 0, 0, v6 },
-{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,       "[i],d", 0, 0, v6 },
-{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),   "[1],d", 0, 0, v6 }, /* lduh [rs1+0],d */
-
-{ "ldx",       F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),      "[1+2],d", 0, 0, v9 },
-{ "ldx",       F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v9 }, /* ldx [rs1+%g0],d */
-{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[1+i],d", 0, 0, v9 },
-{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[i+1],d", 0, 0, v9 },
-{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,       "[i],d", 0, 0, v9 },
-{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),   "[1],d", 0, 0, v9 }, /* ldx [rs1+0],d */
-
-{ "ldx",       F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, v9 },
-{ "ldx",       F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),  "[1],F", 0, 0, v9 }, /* ld [rs1+%g0],d */
-{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, v9 },
-{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, v9 },
-{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),  "[i],F", 0, 0, v9 },
-{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, v9b },
-{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, v9b },
-{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, v9b },
-{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, v9b },
-{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, v9b },
-{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, v9b },
-
-{ "lda",       F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "lda",       F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* lda [rs1+%g0],d */
-{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-{ "lda",       F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2]A,g", 0, 0, v9 },
-{ "lda",       F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1]A,g", 0, 0, v9 }, /* lda [rs1+%g0],d */
-{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i]o,g", 0, 0, v9 },
-{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1]o,g", 0, 0, v9 },
-{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i]o,g", 0, 0, v9 },
-{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1]o,g", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldtwa",     F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", 0, 0, v9 },
-{ "ldtwa",     F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", 0, 0, v9 }, /* ldda [rs1+%g0],d */
-{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", F_ALIAS, 0, v6 },
-{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", F_ALIAS, 0, v6 }, /* ldda [rs1+%g0],d */
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", F_ALIAS, 0, v9 },
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", F_ALIAS, 0, v9 },
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, 0, v9 },
-{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldda",      F3(3, 0x33, 0), F3(~3, ~0x33, ~0),              "[1+2]A,H", 0, 0, v9 },
-{ "ldda",      F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0,       "[1]A,H", 0, 0, v9 }, /* ldda [rs1+%g0],d */
-{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i]o,H", 0, 0, v9 },
-{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1]o,H", 0, 0, v9 },
-{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i]o,H", 0, 0, v9 },
-{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1]o,H", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldqa",      F3(3, 0x32, 0), F3(~3, ~0x32, ~0),              "[1+2]A,J", 0, 0, v9 },
-{ "ldqa",      F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0,       "[1]A,J", 0, 0, v9 }, /* ldd [rs1+%g0],d */
-{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[1+i]o,J", 0, 0, v9 },
-{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[i+1]o,J", 0, 0, v9 },
-{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0,       "[i]o,J", 0, 0, v9 },
-{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0),   "[1]o,J", 0, 0, v9 }, /* ldd [rs1+0],d */
-
-{ "ldsba",     F3(3, 0x19, 0), F3(~3, ~0x19, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "ldsba",     F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* ldsba [rs1+%g0],d */
-{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldsha",     F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "ldsha",     F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* ldsha [rs1+%g0],d */
-{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldstuba",   F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "ldstuba",   F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* ldstuba [rs1+%g0],d */
-{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldswa",     F3(3, 0x18, 0), F3(~3, ~0x18, ~0),              "[1+2]A,d", 0, 0, v9 },
-{ "ldswa",     F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0,       "[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */
-{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "lduba",     F3(3, 0x11, 0), F3(~3, ~0x11, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "lduba",     F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* lduba [rs1+%g0],d */
-{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "lduha",     F3(3, 0x12, 0), F3(~3, ~0x12, ~0),              "[1+2]A,d", 0, 0, v6 },
-{ "lduha",     F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,       "[1]A,d", 0, 0, v6 }, /* lduha [rs1+%g0],d */
-{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "lduwa",     F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", F_ALIAS, 0, v9 }, /* lduwa === lda */
-{ "lduwa",     F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", F_ALIAS, 0, v9 }, /* lda [rs1+%g0],d */
-{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", F_ALIAS, 0, v9 },
-{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", F_ALIAS, 0, v9 },
-{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, 0, v9 },
-{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
-
-{ "ldxa",      F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),              "[1+2]A,d", 0, 0, v9 },
-{ "ldxa",      F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0,       "[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */
-{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
-
-{ "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),              "d,[1+2]", 0, 0, v6 },
-{ "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),          "d,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */
-{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[1+i]", 0, 0, v6 },
-{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[i+1]", 0, 0, v6 },
-{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,               "d,[i]", 0, 0, v6 },
-{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),           "d,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
-{ "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),              "g,[1+2]", 0, 0, v6 },
-{ "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),          "g,[1]", 0, 0, v6 }, /* st d[rs1+%g0] */
-{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[1+i]", 0, 0, v6 },
-{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[i+1]", 0, 0, v6 },
-{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,               "g,[i]", 0, 0, v6 },
-{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),           "g,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
-
-{ "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),              "D,[1+2]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),          "D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
-{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[1+i]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[i+1]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,               "D,[i]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),           "D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */
-{ "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),              "C,[1+2]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),          "C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
-{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[1+i]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[i+1]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,               "C,[i]", 0, 0, v6notv9 },
-{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),           "C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */
-
-{ "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),        "F,[1+2]", 0, 0, v6 },
-{ "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),    "F,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */
-{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[1+i]", 0, 0, v6 },
-{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[i+1]", 0, 0, v6 },
-{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,         "F,[i]", 0, 0, v6 },
-{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),     "F,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
-
-{ "stw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v9 },
-{ "stw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
-{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, v9 },
-{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, v9 },
-{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v9 },
-{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
-{ "stsw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v9 },
-{ "stsw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
-{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, v9 },
-{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, v9 },
-{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v9 },
-{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
-{ "stuw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v9 },
-{ "stuw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
-{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, v9 },
-{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, v9 },
-{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v9 },
-{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
-
-{ "spill",     F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v6 },
-{ "spill",     F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+%g0] */
-{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, v6 },
-{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, v6 },
-{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
-{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+0] */
-
-{ "sta",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", 0, 0, v6 },
-{ "sta",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", 0, 0, v6 }, /* sta d,[rs1+%g0] */
-{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", 0, 0, v9 },
-{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", 0, 0, v9 },
-{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
-{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */
-
-{ "sta",       F3(3, 0x34, 0), F3(~3, ~0x34, ~0),              "g,[1+2]A", 0, 0, v9 },
-{ "sta",       F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0),      "g,[1]A", 0, 0, v9 }, /* sta d,[rs1+%g0] */
-{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[1+i]o", 0, 0, v9 },
-{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[i+1]o", 0, 0, v9 },
-{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,       "g,[i]o", 0, 0, v9 },
-{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),   "g,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */
-
-{ "stwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, 0, v9 },
-{ "stwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
-{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
-{ "stswa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, 0, v9 },
-{ "stswa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
-{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
-{ "stuwa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, 0, v9 },
-{ "stuwa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
-{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
-
-{ "stb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", 0, 0, v6 },
-{ "stb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, v6 }, /* stb d,[rs1+%g0] */
-{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", 0, 0, v6 },
-{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", 0, 0, v6 },
-{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", 0, 0, v6 },
-{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", 0, 0, v6 }, /* stb d,[rs1+0] */
-
-{ "stsb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v6 },
-{ "stsb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */
-{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, 0, v6 },
-{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, 0, v6 },
-{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
-{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */
-{ "stub",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v6 },
-{ "stub",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */
-{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, 0, v6 },
-{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, 0, v6 },
-{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
-{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */
-
-{ "stba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", 0, 0, v6 },
-{ "stba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", 0, 0, v6 }, /* stba d,[rs1+%g0] */
-{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", 0, 0, v9 },
-{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", 0, 0, v9 },
-{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
-{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* stb d,[rs1+0] */
-
-{ "stsba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", F_ALIAS, 0, v6 },
-{ "stsba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */
-{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
-{ "stuba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", F_ALIAS, 0, v6 },
-{ "stuba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */
-{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
-
-{ "sttw",      F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", 0, 0, v9 },
-{ "sttw",      F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, v9 }, /* std d,[rs1+%g0] */
-{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, 0, v9 },
-{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, 0, v9 },
-{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, 0, v9 },
-{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", 0, 0, v9 }, /* std d,[rs1+0] */
-
-{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", F_PREF_ALIAS, 0, v6 },
-{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_PREF_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_PREF_ALIAS, 0, v6 },
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_PREF_ALIAS, 0, v6 },
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_PREF_ALIAS, 0, v6 },
-{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_PREF_ALIAS, 0, v6 }, /* std d,[rs1+0] */
-
-{ "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "q,[1+2]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
-{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[1+i]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[i+1]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "q,[i]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
-{ "std",       F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),      "H,[1+2]", 0, 0, v6 },
-{ "std",       F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),  "H,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */
-{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[1+i]", 0, 0, v6 },
-{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[i+1]", 0, 0, v6 },
-{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,       "H,[i]", 0, 0, v6 },
-{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),   "H,[1]", 0, 0, v6 }, /* std d,[rs1+0] */
-
-{ "std",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "Q,[1+2]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
-{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[1+i]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[i+1]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "Q,[i]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
-{ "std",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),      "D,[1+2]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),  "D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
-{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[1+i]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[i+1]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "D,[i]", 0, 0, v6notv9 },
-{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
-
-{ "spilld",    F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v6 },
-{ "spilld",    F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */
-{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_ALIAS, 0, v6 },
-{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_ALIAS, 0, v6 },
-{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
-{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+0] */
-
-{ "sttwa",     F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", 0, 0, v9 },
-{ "sttwa",     F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
-{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", 0, 0, v9 },
-{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", 0, 0, v9 },
-{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
-{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
-
-{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", F_ALIAS, 0, v6 },
-{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v6 }, /* stda d,[rs1+%g0] */
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* std d,[rs1+0] */
-{ "stda",      F3(3, 0x37, 0), F3(~3, ~0x37, ~0),              "H,[1+2]A", 0, 0, v9 },
-{ "stda",      F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),      "H,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
-{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[1+i]o", 0, 0, v9 },
-{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[i+1]o", 0, 0, v9 },
-{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "H,[i]o", 0, 0, v9 },
-{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "H,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
-
-{ "sth",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", 0, 0, v6 },
-{ "sth",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, v6 }, /* sth d,[rs1+%g0] */
-{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", 0, 0, v6 },
-{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", 0, 0, v6 },
-{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", 0, 0, v6 },
-{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", 0, 0, v6 }, /* sth d,[rs1+0] */
-
-{ "stsh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v6 },
-{ "stsh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */
-{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, 0, v6 },
-{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, 0, v6 },
-{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
-{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */
-{ "stuh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, v6 },
-{ "stuh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */
-{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, 0, v6 },
-{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, 0, v6 },
-{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, v6 },
-{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */
-
-{ "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", 0, 0, v6 },
-{ "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", 0, 0, v6 }, /* stha ,[rs1+%g0] */
-{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", 0, 0, v9 },
-{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", 0, 0, v9 },
-{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
-{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* sth d,[rs1+0] */
-
-{ "stsha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", F_ALIAS, 0, v6 },
-{ "stsha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */
-{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */
-{ "stuha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", F_ALIAS, 0, v6 },
-{ "stuha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */
-{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, 0, v9 },
-{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, 0, v9 },
-{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, v9 },
-{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */
-
-{ "stx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),      "d,[1+2]", 0, 0, v9 },
-{ "stx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */
-{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[1+i]", 0, 0, v9 },
-{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[i+1]", 0, 0, v9 },
-{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0,       "d,[i]", 0, 0, v9 },
-{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),   "d,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */
-
-{ "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, v9 },
-{ "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */
-{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[1+i]", 0, 0, v9 },
-{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[i+1]", 0, 0, v9 },
-{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),  "F,[i]", 0, 0, v9 },
-{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */
-
-{ "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),              "d,[1+2]A", 0, 0, v9 },
-{ "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),      "d,[1]A", 0, 0, v9 }, /* stxa d,[rs1+%g0] */
-{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[1+i]o", 0, 0, v9 },
-{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[i+1]o", 0, 0, v9 },
-{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,       "d,[i]o", 0, 0, v9 },
-{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, v9 }, /* stx d,[rs1+0] */
-
-{ "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "J,[1+2]", 0, 0, v9 },
-{ "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "J,[1]", 0, 0, v9 }, /* stq [rs1+%g0] */
-{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[1+i]", 0, 0, v9 },
-{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[i+1]", 0, 0, v9 },
-{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "J,[i]", 0, 0, v9 },
-{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "J,[1]", 0, 0, v9 }, /* stq [rs1+0] */
-
-{ "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "J,[1+2]A", 0, 0, v9 },
-{ "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "J,[1]A", 0, 0, v9 }, /* stqa [rs1+%g0] */
-{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[1+i]o", 0, 0, v9 },
-{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[i+1]o", 0, 0, v9 },
-{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "J,[i]o", 0, 0, v9 },
-{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "J,[1]o", 0, 0, v9 }, /* stqa [rs1+0] */
-
-{ "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),      "[1+2],d", 0, 0, v7 },
-{ "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, v7 }, /* swap [rs1+%g0],d */
-{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[1+i],d", 0, 0, v7 },
-{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[i+1],d", 0, 0, v7 },
-{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,       "[i],d", 0, 0, v7 },
-{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),   "[1],d", 0, 0, v7 }, /* swap [rs1+0],d */
-
-{ "swapa",     F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),              "[1+2]A,d", 0, 0, v7 },
-{ "swapa",     F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),      "[1]A,d", 0, 0, v7 }, /* swapa [rs1+%g0],d */
-{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[1+i]o,d", 0, 0, v9 },
-{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[i+1]o,d", 0, 0, v9 },
-{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0,       "[i]o,d", 0, 0, v9 },
-{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, v9 }, /* swap [rs1+0],d */
-
-{ "restore",   F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),                      "1,2,d", 0, 0, v6 },
-{ "restore",   F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, 0, v6 }, /* restore %g0,%g0,%g0 */
-{ "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                              "1,i,d", 0, 0, v6 },
-{ "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),      "", 0, 0, v6 }, /* restore %g0,0,%g0 */
-
-{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+rs2 */
-{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1,%g0 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+X */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+0 */
-
-{ "save",      F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, 0, v6 },
-{ "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "i,1,d", 0, 0, v6 }, /* Sun assembler compatibility */
-{ "save",      0x81e00000,     ~0x81e00000,                    "", F_ALIAS, 0, v6 },
-
-{ "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),           "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %i7+8,%g0 */
-{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %o7+8,%g0 */
-
-{ "jmpl",      F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),      "1+2,d", F_JSR|F_DELAYED, 0, v6 },
-{ "jmpl",      F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),  "1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,d */
-{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),   "1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,d */
-{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,       "i,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,d */
-{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "1+i,d", F_JSR|F_DELAYED, 0, v6 },
-{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "i+1,d", F_JSR|F_DELAYED, 0, v6 },
-
-{ "done",      F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "retry",     F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "saved",     F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "restored",  F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "allclean",  F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "otherw",    F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "normalw",   F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "invalw",    F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0),       "", 0, 0, v9 },
-{ "sir",       F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,              "i", 0, 0, v9 },
-
-{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "[1+2]", 0, 0, v9 },
-{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "[1]", 0, 0, v9 }, /* flush rs1+%g0 */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "[1]", 0, 0, v9 }, /* flush rs1+0 */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "[i]", 0, 0, v9 }, /* flush %g0+i */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "[1+i]", 0, 0, v9 },
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "[i+1]", 0, 0, v9 },
-
-{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, 0, v8 },
-{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, v8 }, /* flush rs1+%g0 */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, 0, v8 }, /* flush rs1+0 */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, 0, v8 }, /* flush %g0+i */
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, 0, v8 },
-{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, 0, v8 },
+{ "lduw",      F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", F_ALIAS, 0, 0, v9 },
+{ "lduw",      F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+%g0],d */
+{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", F_ALIAS, 0, 0, v9 },
+{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", F_ALIAS, 0, 0, v9 },
+{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", F_ALIAS, 0, 0, v9 },
+{ "lduw",      F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldtw",      F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v9 },
+{ "ldtw",      F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+0],d */
+
+{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),      "[1+2],d", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),   "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */
+{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),      "[1+2],H", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", F_ALIAS, 0, 0, v6 },
+{ "ldd",       F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),   "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */
+
+{ "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),      "[1+2],D", 0, 0, 0, v6notv9 },
+{ "ldd",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */
+{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i],D", 0, 0, 0, v6notv9 },
+{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1],D", 0, 0, 0, v6notv9 },
+{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i],D", 0, 0, 0, v6notv9 },
+{ "ldd",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+0],d */
+
+{ "ldq",       F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),      "[1+2],J", 0, 0, 0, v9 },
+{ "ldq",       F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),  "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */
+{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[1+i],J", 0, 0, 0, v9 },
+{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[i+1],J", 0, 0, 0, v9 },
+{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,       "[i],J", 0, 0, 0, v9 },
+{ "ldq",       F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),   "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */
+
+{ "ldsb",      F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v6 },
+{ "ldsb",      F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+%g0],d */
+{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[1+i],d", 0, 0, 0, v6 },
+{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[i+1],d", 0, 0, 0, v6 },
+{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v6 },
+{ "ldsb",      F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+0],d */
+
+{ "ldsh",      F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+%g0],d */
+{ "ldsh",      F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v6 },
+{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[1+i],d", 0, 0, 0, v6 },
+{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[i+1],d", 0, 0, 0, v6 },
+{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v6 },
+{ "ldsh",      F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+0],d */
+
+{ "ldstub",    F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v6 },
+{ "ldstub",    F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+%g0],d */
+{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[1+i],d", 0, 0, 0, v6 },
+{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[i+1],d", 0, 0, 0, v6 },
+{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v6 },
+{ "ldstub",    F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+0],d */
+
+{ "ldsw",      F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v9 },
+{ "ldsw",      F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+%g0],d */
+{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[1+i],d", 0, 0, 0, v9 },
+{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[i+1],d", 0, 0, 0, v9 },
+{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v9 },
+{ "ldsw",      F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+0],d */
+
+{ "ldub",      F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v6 },
+{ "ldub",      F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+%g0],d */
+{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[1+i],d", 0, 0, 0, v6 },
+{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[i+1],d", 0, 0, 0, v6 },
+{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v6 },
+{ "ldub",      F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+0],d */
+
+{ "lduh",      F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v6 },
+{ "lduh",      F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+%g0],d */
+{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[1+i],d", 0, 0, 0, v6 },
+{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[i+1],d", 0, 0, 0, v6 },
+{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v6 },
+{ "lduh",      F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+0],d */
+
+{ "ldx",       F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+%g0],d */
+{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[1+i],d", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[i+1],d", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+0],d */
+
+{ "ldx",       F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),  "[1],F", 0, 0, 0, v9 }, /* ld [rs1+%g0],d */
+{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),  "[i],F", 0, 0, 0, v9 },
+{ "ldx",       F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, 0, v9b },
+{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, 0, v9b },
+{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, 0, v9b },
+{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, 0, v9b },
+{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, 0, v9b },
+{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, 0, v9b },
+
+{ "lda",       F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", 0, 0, 0, v6 },
+{ "lda",       F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v6 }, /* lda [rs1+%g0],d */
+{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+{ "lda",       F3(3, 0x30, 0), F3(~3, ~0x30, ~0),              "[1+2]A,g", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,       "[1]A,g", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */
+{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i]o,g", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1]o,g", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i]o,g", 0, 0, 0, v9 },
+{ "lda",       F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),   "[1]o,g", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldtwa",     F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", 0, 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "ldtwa",     F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0),              "[1+2]A,d", F_ALIAS, 0, 0, v6 },
+{ "ldda",      F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,       "[1]A,d", F_ALIAS, 0, 0, v6 }, /* ldda [rs1+%g0],d */
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", F_ALIAS, 0, 0, v9 },
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", F_ALIAS, 0, 0, v9 },
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, 0, 0, v9 },
+{ "ldda",      F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),   "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldda",      F3(3, 0x33, 0), F3(~3, ~0x33, ~0),              "[1+2]A,H", 0, 0, 0, v9 },
+{ "ldda",      F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0,       "[1]A,H", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */
+{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i]o,H", 0, 0, 0, v9 },
+{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1]o,H", 0, 0, 0, v9 },
+{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i]o,H", 0, 0, 0, v9 },
+{ "ldda",      F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),   "[1]o,H", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldqa",      F3(3, 0x32, 0), F3(~3, ~0x32, ~0),              "[1+2]A,J", 0, 0, 0, v9 },
+{ "ldqa",      F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0,       "[1]A,J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */
+{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[1+i]o,J", 0, 0, 0, v9 },
+{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[i+1]o,J", 0, 0, 0, v9 },
+{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0,       "[i]o,J", 0, 0, 0, v9 },
+{ "ldqa",      F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0),   "[1]o,J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */
+
+{ "ldsba",     F3(3, 0x19, 0), F3(~3, ~0x19, ~0),              "[1+2]A,d", 0, 0, 0, v6 },
+{ "ldsba",     F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v6 }, /* ldsba [rs1+%g0],d */
+{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "ldsba",     F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldsha",     F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),              "[1+2]A,d", 0, 0, 0, v6 },
+{ "ldsha",     F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v6 }, /* ldsha [rs1+%g0],d */
+{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "ldsha",     F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldstuba",   F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),              "[1+2]A,d", 0, 0, 0, v6 },
+{ "ldstuba",   F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v6 }, /* ldstuba [rs1+%g0],d */
+{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "ldstuba",   F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldswa",     F3(3, 0x18, 0), F3(~3, ~0x18, ~0),              "[1+2]A,d", 0, 0, 0, v9 },
+{ "ldswa",     F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */
+{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "ldswa",     F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "lduba",     F3(3, 0x11, 0), F3(~3, ~0x11, ~0),              "[1+2]A,d", 0, 0, 0, v6 },
+{ "lduba",     F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v6 }, /* lduba [rs1+%g0],d */
+{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "lduba",     F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "lduha",     F3(3, 0x12, 0), F3(~3, ~0x12, ~0),              "[1+2]A,d", 0, 0, 0, v6 },
+{ "lduha",     F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v6 }, /* lduha [rs1+%g0],d */
+{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "lduha",     F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "lduwa",     F3(3, 0x10, 0), F3(~3, ~0x10, ~0),              "[1+2]A,d", F_ALIAS, 0, 0, v9 }, /* lduwa === lda */
+{ "lduwa",     F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,       "[1]A,d", F_ALIAS, 0, 0, v9 }, /* lda [rs1+%g0],d */
+{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", F_ALIAS, 0, 0, v9 },
+{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", F_ALIAS, 0, 0, v9 },
+{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, 0, 0, v9 },
+{ "lduwa",     F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),   "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "ldxa",      F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),              "[1+2]A,d", 0, 0, 0, v9 },
+{ "ldxa",      F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0,       "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */
+{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "ldxa",      F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */
+
+{ "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),              "d,[1+2]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),          "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */
+{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[1+i]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[i+1]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,               "d,[i]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),           "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
+{ "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),              "g,[1+2]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),          "g,[1]", 0, 0, 0, v6 }, /* st d[rs1+%g0] */
+{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[1+i]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[i+1]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,               "g,[i]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),           "g,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
+
+{ "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),              "D,[1+2]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),          "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
+{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[1+i]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[i+1]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,               "D,[i]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),           "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */
+{ "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),              "C,[1+2]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),          "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
+{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[1+i]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[i+1]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,               "C,[i]", 0, 0, 0, v6notv9 },
+{ "st",        F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),           "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */
+
+{ "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),        "F,[1+2]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),    "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */
+{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[1+i]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[i+1]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,         "F,[i]", 0, 0, 0, v6 },
+{ "st",        F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),     "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */
+
+{ "stw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v9 },
+{ "stw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */
+{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v9 },
+{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v9 },
+{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v9 },
+{ "stw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
+{ "stsw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v9 },
+{ "stsw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */
+{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v9 },
+{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v9 },
+{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v9 },
+{ "stsw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
+{ "stuw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v9 },
+{ "stuw",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */
+{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v9 },
+{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v9 },
+{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v9 },
+{ "stuw",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
+
+{ "spill",     F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v6 },
+{ "spill",     F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+%g0] */
+{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v6 },
+{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v6 },
+{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v6 },
+{ "spill",     F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+0] */
+
+{ "sta",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", 0, 0, 0, v6 },
+{ "sta",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", 0, 0, 0, v6 }, /* sta d,[rs1+%g0] */
+{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */
+
+{ "sta",       F3(3, 0x34, 0), F3(~3, ~0x34, ~0),              "g,[1+2]A", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0),      "g,[1]A", 0, 0, 0, v9 }, /* sta d,[rs1+%g0] */
+{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[1+i]o", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[i+1]o", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,       "g,[i]o", 0, 0, 0, v9 },
+{ "sta",       F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),   "g,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */
+
+{ "stwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v9 },
+{ "stwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */
+{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
+{ "stswa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v9 },
+{ "stswa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */
+{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stswa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
+{ "stuwa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v9 },
+{ "stuwa",     F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */
+{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stuwa",     F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */
+
+{ "stb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", 0, 0, 0, v6 },
+{ "stb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+%g0] */
+{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", 0, 0, 0, v6 },
+{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", 0, 0, 0, v6 },
+{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", 0, 0, 0, v6 },
+{ "stb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+0] */
+
+{ "stsb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v6 },
+{ "stsb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */
+{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v6 },
+{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v6 },
+{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v6 },
+{ "stsb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */
+{ "stub",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v6 },
+{ "stub",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */
+{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v6 },
+{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v6 },
+{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v6 },
+{ "stub",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */
+
+{ "stba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", 0, 0, 0, v6 },
+{ "stba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", 0, 0, 0, v6 }, /* stba d,[rs1+%g0] */
+{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", 0, 0, 0, v9 },
+{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", 0, 0, 0, v9 },
+{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", 0, 0, 0, v9 },
+{ "stba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, 0, v9 }, /* stb d,[rs1+0] */
+
+{ "stsba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v6 },
+{ "stsba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */
+{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stsba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */
+{ "stuba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v6 },
+{ "stuba",     F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */
+{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stuba",     F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */
+
+{ "sttw",      F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", 0, 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+%g0] */
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, 0, 0, v9 },
+{ "sttw",      F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+0] */
+
+{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", F_PREF_ALIAS, 0, 0, v6 },
+{ "std",       F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_PREF_ALIAS, 0, 0, v6 },
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_PREF_ALIAS, 0, 0, v6 },
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_PREF_ALIAS, 0, 0, v6 },
+{ "std",       F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */
+
+{ "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "q,[1+2]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
+{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[1+i]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[i+1]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "q,[i]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */
+{ "std",       F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),      "H,[1+2]", 0, 0, 0, v6 },
+{ "std",       F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),  "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+%g0] */
+{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[1+i]", 0, 0, 0, v6 },
+{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[i+1]", 0, 0, 0, v6 },
+{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,       "H,[i]", 0, 0, 0, v6 },
+{ "std",       F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),   "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+0] */
+
+{ "std",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "Q,[1+2]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
+{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[1+i]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[i+1]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "Q,[i]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */
+{ "std",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),      "D,[1+2]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),  "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
+{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[1+i]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[i+1]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "D,[i]", 0, 0, 0, v6notv9 },
+{ "std",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */
+
+{ "spilld",    F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v6 },
+{ "spilld",    F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */
+{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v6 },
+{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v6 },
+{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v6 },
+{ "spilld",    F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */
+
+{ "sttwa",     F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", 0, 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", 0, 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", 0, 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", 0, 0, 0, v9 },
+{ "sttwa",     F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */
+
+{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v6 },
+{ "stda",      F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stda d,[rs1+%g0] */
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stda",      F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* std d,[rs1+0] */
+{ "stda",      F3(3, 0x37, 0), F3(~3, ~0x37, ~0),              "H,[1+2]A", 0, 0, 0, v9 },
+{ "stda",      F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),      "H,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */
+{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[1+i]o", 0, 0, 0, v9 },
+{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[i+1]o", 0, 0, 0, v9 },
+{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "H,[i]o", 0, 0, 0, v9 },
+{ "stda",      F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),   "H,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */
+
+{ "sth",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", 0, 0, 0, v6 },
+{ "sth",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+%g0] */
+{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", 0, 0, 0, v6 },
+{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", 0, 0, 0, v6 },
+{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", 0, 0, 0, v6 },
+{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+0] */
+
+{ "stsh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v6 },
+{ "stsh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */
+{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v6 },
+{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v6 },
+{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v6 },
+{ "stsh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */
+{ "stuh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),      "d,[1+2]", F_ALIAS, 0, 0, v6 },
+{ "stuh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */
+{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, 0, 0, v6 },
+{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, 0, 0, v6 },
+{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, 0, 0, v6 },
+{ "stuh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */
+
+{ "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", 0, 0, 0, v6 },
+{ "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", 0, 0, 0, v6 }, /* stha ,[rs1+%g0] */
+{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", 0, 0, 0, v9 },
+{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", 0, 0, 0, v9 },
+{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", 0, 0, 0, v9 },
+{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, 0, v9 }, /* sth d,[rs1+0] */
+
+{ "stsha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v6 },
+{ "stsha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */
+{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stsha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */
+{ "stuha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", F_ALIAS, 0, 0, v6 },
+{ "stuha",     F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */
+{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, 0, 0, v9 },
+{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, 0, 0, v9 },
+{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, 0, 0, v9 },
+{ "stuha",     F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */
+
+{ "stx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),      "d,[1+2]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */
+{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[1+i]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[i+1]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0,       "d,[i]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),   "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */
+
+{ "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */
+{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[1+i]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[i+1]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),  "F,[i]", 0, 0, 0, v9 },
+{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */
+
+{ "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),              "d,[1+2]A", 0, 0, 0, v9 },
+{ "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),      "d,[1]A", 0, 0, 0, v9 }, /* stxa d,[rs1+%g0] */
+{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[1+i]o", 0, 0, 0, v9 },
+{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[i+1]o", 0, 0, 0, v9 },
+{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,       "d,[i]o", 0, 0, 0, v9 },
+{ "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),   "d,[1]o", 0, 0, 0, v9 }, /* stx d,[rs1+0] */
+
+{ "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "J,[1+2]", 0, 0, 0, v9 },
+{ "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+%g0] */
+{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[1+i]", 0, 0, 0, v9 },
+{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[i+1]", 0, 0, 0, v9 },
+{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "J,[i]", 0, 0, 0, v9 },
+{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+0] */
+
+{ "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "J,[1+2]A", 0, 0, 0, v9 },
+{ "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "J,[1]A", 0, 0, 0, v9 }, /* stqa [rs1+%g0] */
+{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[1+i]o", 0, 0, 0, v9 },
+{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[i+1]o", 0, 0, 0, v9 },
+{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "J,[i]o", 0, 0, 0, v9 },
+{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "J,[1]o", 0, 0, 0, v9 }, /* stqa [rs1+0] */
+
+{ "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),      "[1+2],d", 0, 0, 0, v7 },
+{ "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v7 }, /* swap [rs1+%g0],d */
+{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[1+i],d", 0, 0, 0, v7 },
+{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[i+1],d", 0, 0, 0, v7 },
+{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,       "[i],d", 0, 0, 0, v7 },
+{ "swap",      F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),   "[1],d", 0, 0, 0, v7 }, /* swap [rs1+0],d */
+
+{ "swapa",     F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),              "[1+2]A,d", 0, 0, 0, v7 },
+{ "swapa",     F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),      "[1]A,d", 0, 0, 0, v7 }, /* swapa [rs1+%g0],d */
+{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[1+i]o,d", 0, 0, 0, v9 },
+{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[i+1]o,d", 0, 0, 0, v9 },
+{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0,       "[i]o,d", 0, 0, 0, v9 },
+{ "swapa",     F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0),   "[1]o,d", 0, 0, 0, v9 }, /* swap [rs1+0],d */
+
+{ "restore",   F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),                      "1,2,d", 0, 0, 0, v6 },
+{ "restore",   F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, 0, 0, v6 }, /* restore %g0,%g0,%g0 */
+{ "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                              "1,i,d", 0, 0, 0, v6 },
+{ "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),      "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */
+
+{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+rs2 */
+{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, 0, 0, v6 },      /* rett rs1,%g0 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+X */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6 },      /* rett X */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, 0, 0, v6 },      /* rett rs1+0 */
+
+{ "save",      F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "i,1,d", 0, 0, 0, v6 }, /* Sun assembler compatibility */
+{ "save",      0x81e00000,     ~0x81e00000,                    "", F_ALIAS, 0, 0, v6 },
+
+{ "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),           "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %i7+8,%g0 */
+{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %o7+8,%g0 */
+
+{ "jmpl",      F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),      "1+2,d", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "jmpl",      F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),  "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,d */
+{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),   "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,d */
+{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,       "i,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,d */
+{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "1+i,d", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "jmpl",      F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "i+1,d", F_JSR|F_DELAYED, 0, 0, v6 },
+
+{ "done",      F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "retry",     F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "saved",     F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "restored",  F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "allclean",  F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "otherw",    F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "normalw",   F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "invalw",    F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0),       "", 0, 0, 0, v9 },
+{ "sir",       F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,              "i", 0, 0, 0, v9 },
+
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "[1+2]", 0, 0, 0, v9 },
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "[1]", 0, 0, 0, v9 }, /* flush rs1+%g0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "[1]", 0, 0, 0, v9 }, /* flush rs1+0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "[i]", 0, 0, 0, v9 }, /* flush %g0+i */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "[1+i]", 0, 0, 0, v9 },
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "[i+1]", 0, 0, 0, v9 },
+
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, 0, 0, v8 },
+{ "flush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, 0, 0, v8 },
+{ "flush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, 0, 0, v8 },
 
 /* IFLUSH was renamed to FLUSH in v8.  */
-{ "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, 0, v6 },
-{ "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, v6 }, /* flush rs1+%g0 */
-{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, 0, v6 }, /* flush rs1+0 */
-{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, 0, v6 },
-{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, 0, v6 },
-{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, 0, v6 },
-
-{ "return",    F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0),      "1+2", 0, 0, v9 },
-{ "return",    F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),  "1", 0, 0, v9 }, /* return rs1+%g0 */
-{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0),   "1", 0, 0, v9 }, /* return rs1+0 */
-{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0,       "i", 0, 0, v9 }, /* return %g0+i */
-{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "1+i", 0, 0, v9 },
-{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "i+1", 0, 0, v9 },
-
-{ "flushw",    F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, 0, v9 },
-
-{ "membar",    F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, v9 },
-{ "stbar",     F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, v8 },
-
-{ "prefetch",  F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),              "[1+2],*", 0, 0, v9 },
-{ "prefetch",  F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0,       "[1],*", 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
-{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[1+i],*", 0, 0, v9 },
-{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[i+1],*", 0, 0, v9 },
-{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,       "[i],*", 0, 0, v9 },
-{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),   "[1],*", 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
-{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),              "[1+2]A,*", 0, 0, v9 },
-{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0,       "[1]A,*", 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
-{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[1+i]o,*", 0, 0, v9 },
-{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[i+1]o,*", 0, 0, v9 },
-{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,       "[i]o,*", 0, 0, v9 },
-{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),   "[1]o,*", 0, 0, v9 }, /* prefetcha [rs1+0],d */
-
-{ "sll",       F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, 0, v6 },
-{ "sll",       F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, 0, v6 },
-{ "sra",       F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, 0, v6 },
-{ "sra",       F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, 0, v6 },
-{ "srl",       F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, 0, v6 },
-{ "srl",       F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, 0, v6 },
-
-{ "sllx",      F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),    "1,2,d", 0, 0, v9 },
-{ "sllx",      F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),    "1,Y,d", 0, 0, v9 },
-{ "srax",      F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),    "1,2,d", 0, 0, v9 },
-{ "srax",      F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),    "1,Y,d", 0, 0, v9 },
-{ "srlx",      F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),    "1,2,d", 0, 0, v9 },
-{ "srlx",      F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),    "1,Y,d", 0, 0, v9 },
-
-{ "mulscc",    F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "mulscc",    F3(2, 0x24, 1), F3(~2, ~0x24, ~1),              "1,i,d", 0, 0, v6 },
-
-{ "divscc",    F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),      "1,2,d", 0, 0, sparclite },
-{ "divscc",    F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),              "1,i,d", 0, 0, sparclite },
-
-{ "scan",      F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),      "1,2,d", 0, 0, sparclet|sparclite },
-{ "scan",      F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),              "1,i,d", 0, 0, sparclet|sparclite },
-
-{ "popc",      F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, v9 },
-{ "popc",      F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,       "i,d", 0, HWCAP_POPC, v9 },
-
-{ "clr",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "d", F_ALIAS, 0, v6 }, /* or %g0,%g0,d */
-{ "clr",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),            "d", F_ALIAS, 0, v6 }, /* or %g0,0,d    */
-{ "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),                "[1+2]", F_ALIAS, 0, v6 },
-{ "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),            "[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+%g0] */
-{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, 0, v6 },
-{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, 0, v6 },
-{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,                 "[i]", F_ALIAS, 0, v6 },
-{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),             "[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+0] */
-
-{ "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, 0, v6 },
-{ "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+%g0] */
-{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, 0, v6 },
-{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, 0, v6 },
-{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, 0, v6 },
-{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+0] */
-
-{ "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, 0, v6 },
-{ "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+%g0] */
-{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, 0, v6 },
-{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, 0, v6 },
-{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, 0, v6 },
-{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+0] */
-
-{ "clrx",      F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, 0, v9 },
-{ "clrx",      F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+%g0] */
-{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[1+i]", F_ALIAS, 0, v9 },
-{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[i+1]", F_ALIAS, 0, v9 },
-{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, 0, v9 },
-{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+0] */
-
-{ "orcc",      F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "1,i,d", 0, 0, v6 },
-{ "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "i,1,d", 0, 0, v6 },
+{ "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),      "1+2", F_ALIAS, 0, 0, v6 },
+{ "iflush",    F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+%g0 */
+{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),   "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+0 */
+{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, 0, 0, v6 },
+{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, 0, 0, v6 },
+{ "iflush",    F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, 0, 0, v6 },
+
+{ "return",    F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0),      "1+2", 0, 0, 0, v9 },
+{ "return",    F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),  "1", 0, 0, 0, v9 }, /* return rs1+%g0 */
+{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0),   "1", 0, 0, 0, v9 }, /* return rs1+0 */
+{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0,       "i", 0, 0, 0, v9 }, /* return %g0+i */
+{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "1+i", 0, 0, 0, v9 },
+{ "return",    F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "i+1", 0, 0, 0, v9 },
+
+{ "flushw",    F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "", 0, 0, 0, v9 },
+
+{ "membar",    F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9 },
+{ "stbar",     F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8 },
+
+{ "prefetch",  F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),              "[1+2],*", 0, 0, 0, v9 },
+{ "prefetch",  F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0,       "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
+{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[1+i],*", 0, 0, 0, v9 },
+{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[i+1],*", 0, 0, 0, v9 },
+{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,       "[i],*", 0, 0, 0, v9 },
+{ "prefetch",  F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),   "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
+{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),              "[1+2]A,*", 0, 0, 0, v9 },
+{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0,       "[1]A,*", 0, 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
+{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[1+i]o,*", 0, 0, 0, v9 },
+{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[i+1]o,*", 0, 0, 0, v9 },
+{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,       "[i]o,*", 0, 0, 0, v9 },
+{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),   "[1]o,*", 0, 0, 0, v9 }, /* prefetcha [rs1+0],d */
+
+{ "sll",       F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, 0, 0, v6 },
+{ "sll",       F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, 0, 0, v6 },
+{ "sra",       F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, 0, 0, v6 },
+{ "sra",       F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, 0, 0, v6 },
+{ "srl",       F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),    "1,2,d", 0, 0, 0, v6 },
+{ "srl",       F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, 0, 0, v6 },
+
+{ "sllx",      F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),    "1,2,d", 0, 0, 0, v9 },
+{ "sllx",      F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),    "1,Y,d", 0, 0, 0, v9 },
+{ "srax",      F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),    "1,2,d", 0, 0, 0, v9 },
+{ "srax",      F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),    "1,Y,d", 0, 0, 0, v9 },
+{ "srlx",      F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),    "1,2,d", 0, 0, 0, v9 },
+{ "srlx",      F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),    "1,Y,d", 0, 0, 0, v9 },
+
+{ "mulscc",    F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "mulscc",    F3(2, 0x24, 1), F3(~2, ~0x24, ~1),              "1,i,d", 0, 0, 0, v6 },
+
+{ "divscc",    F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, sparclite },
+{ "divscc",    F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),              "1,i,d", 0, 0, 0, sparclite },
+
+{ "scan",      F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, sparclet|sparclite },
+{ "scan",      F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),              "1,i,d", 0, 0, 0, sparclet|sparclite },
+
+{ "popc",      F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, 0, v9 },
+{ "popc",      F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,       "i,d", 0, HWCAP_POPC, 0, v9 },
+
+{ "clr",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),     "d", F_ALIAS, 0, 0, v6 }, /* or %g0,%g0,d */
+{ "clr",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),            "d", F_ALIAS, 0, 0, v6 }, /* or %g0,0,d */
+{ "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),                "[1+2]", F_ALIAS, 0, 0, v6 },
+{ "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),            "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+%g0] */
+{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, 0, 0, v6 },
+{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, 0, 0, v6 },
+{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,                 "[i]", F_ALIAS, 0, 0, v6 },
+{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),             "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+0] */
+
+{ "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, 0, 0, v6 },
+{ "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+%g0] */
+{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, 0, 0, v6 },
+{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, 0, 0, v6 },
+{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, 0, 0, v6 },
+{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+0] */
+
+{ "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, 0, 0, v6 },
+{ "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+%g0] */
+{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, 0, 0, v6 },
+{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, 0, 0, v6 },
+{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, 0, 0, v6 },
+{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+0] */
+
+{ "clrx",      F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, 0, 0, v9 },
+{ "clrx",      F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+%g0] */
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[1+i]", F_ALIAS, 0, 0, v9 },
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[i+1]", F_ALIAS, 0, 0, v9 },
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, 0, 0, v9 },
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+0] */
+
+{ "orcc",      F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "i,1,d", 0, 0, 0, v6 },
 
 /* This is not a commutative instruction.  */
-{ "orncc",     F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "orncc",     F3(2, 0x16, 1), F3(~2, ~0x16, ~1),              "1,i,d", 0, 0, v6 },
+{ "orncc",     F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "orncc",     F3(2, 0x16, 1), F3(~2, ~0x16, ~1),              "1,i,d", 0, 0, 0, v6 },
 
 /* This is not a commutative instruction.  */
-{ "orn",       F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "orn",       F3(2, 0x06, 1), F3(~2, ~0x06, ~1),              "1,i,d", 0, 0, v6 },
-
-{ "tst",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),    "1", 0, 0, v6 }, /* orcc rs1, %g0, %g0 */
-{ "tst",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, v6 }, /* orcc %g0, rs2, %g0 */
-{ "tst",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),     "1", 0, 0, v6 }, /* orcc rs1, 0, %g0 */
-
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", 0, 0, v8 }, /* wr r,r,%asrX */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", 0, 0, v8 }, /* wr r,i,%asrX */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_PREF_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_PREF_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|SIMM13(~0),           "1,m", F_PREF_ALIAS, 0, v8 }, /* wr rs1,%asrX */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_PREF_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", 0, 0, v6 }, /* wr r,r,%y */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, 0, v6 }, /* wr r,i,%y */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_PREF_ALIAS, 0, v6 }, /* wr %g0,i,%y */
-{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),     "1,y", F_PREF_ALIAS, 0, v6 }, /* wr rs1,0,%y */
-{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_PREF_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
-{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", 0, 0, v6notv9 }, /* wr r,r,%psr */
-{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", 0, 0, v6notv9 }, /* wr r,i,%psr */
-{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
-{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
-{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),     "1,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%psr */
-{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
-{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", 0, 0, v6notv9 }, /* wr r,r,%wim */
-{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", 0, 0, v6notv9 }, /* wr r,i,%wim */
-{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
-{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
-{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),     "1,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%wim */
-{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
-{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", 0, 0, v6notv9 }, /* wr r,r,%tbr */
-{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", 0, 0, v6notv9 }, /* wr r,i,%tbr */
-{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
-{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
-{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),     "1,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%tbr */
-{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
-
-{ "wr", F3(2, 0x30, 0)|RD(2),  F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),       "1,2,E", 0, 0, v9 }, /* wr r,r,%ccr */
-{ "wr", F3(2, 0x30, 1)|RD(2),  F3(~2, ~0x30, ~1)|RD(~2),               "1,i,E", 0, 0, v9 }, /* wr r,i,%ccr */
-{ "wr", F3(2, 0x30, 0)|RD(3),  F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),       "1,2,o", 0, 0, v9 }, /* wr r,r,%asi */
-{ "wr", F3(2, 0x30, 1)|RD(3),  F3(~2, ~0x30, ~1)|RD(~3),               "1,i,o", 0, 0, v9 }, /* wr r,i,%asi */
-{ "wr", F3(2, 0x30, 0)|RD(6),  F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),       "1,2,s", 0, 0, v9 }, /* wr r,r,%fprs */
-{ "wr", F3(2, 0x30, 1)|RD(6),  F3(~2, ~0x30, ~1)|RD(~6),               "1,i,s", 0, 0, v9 }, /* wr r,i,%fprs */
-
-{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pcr */
-{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pcr */
-{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pic */
-{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pic */
-{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%dcr */
-{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%dcr */
-{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%gsr */
-{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%gsr */
-{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%set_softint */
-{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%set_softint */
-{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%clear_softint */
-{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%clear_softint */
-{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%softint */
-{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%softint */
-{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%tick_cmpr */
-{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23),              "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%tick_cmpr */
-{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),      "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick */
-{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24),              "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */
-{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),      "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */
-{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25),              "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */
-{ "wr", F3(2, 0x30, 0)|RD(26), F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0),      "1,2,_", 0, HWCAP_CBCOND, v9b }, /* wr r,r,%cfr */
-{ "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26),              "1,i,_", 0, HWCAP_CBCOND, v9b }, /* wr r,i,%cfr */
-{ "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0),      "1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */
-{ "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27),              "1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */
-{ "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0),      "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */
-{ "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28),              "1,i,_", 0, HWCAP_VIS3, v9b }, /* wr r,i,%cps */
-
-{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, v9b }, /* wr %g0,i,%pause */
-
-{ "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", 0, 0, v8 }, /* rd %asrX,r */
-{ "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", 0, 0, v6 }, /* rd %y,r */
-{ "rd",        F3(2, 0x29, 0),                 F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", 0, 0, v6notv9 }, /* rd %psr,r */
-{ "rd",        F3(2, 0x2a, 0),                 F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", 0, 0, v6notv9 }, /* rd %wim,r */
-{ "rd",        F3(2, 0x2b, 0),                 F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", 0, 0, v6notv9 }, /* rd %tbr,r */
-
-{ "rd",        F3(2, 0x28, 0)|RS1(2),          F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),   "E,d", 0, 0, v9 }, /* rd %ccr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(3),          F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0),   "o,d", 0, 0, v9 }, /* rd %asi,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(4),          F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),   "W,d", 0, 0, v9 }, /* rd %tick,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(5),          F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),   "P,d", 0, 0, v9 }, /* rd %pc,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(6),          F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),   "s,d", 0, 0, v9 }, /* rd %fprs,r */
-
-{ "rd",        F3(2, 0x28, 0)|RS1(16),         F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %pcr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(17),         F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %pic,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(18),         F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %dcr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(19),         F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %gsr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(22),         F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %softint,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(23),         F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(24),         F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),  "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(25),         F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),  "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick_cmpr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(26),         F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0),  "/,d", 0, HWCAP_CBCOND, v9b }, /* rd %cfr,r */
-{ "rd",        F3(2, 0x28, 0)|RS1(28),         F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0),  "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */
-
-{ "rdpr",      F3(2, 0x2a, 0),         F3(~2, ~0x2a, ~0)|SIMM13(~0),   "?,d", 0, 0, v9 },   /* rdpr %priv,r */
-{ "wrpr",      F3(2, 0x32, 0),         F3(~2, ~0x32, ~0),              "1,2,!", 0, 0, v9 }, /* wrpr r1,r2,%priv */
-{ "wrpr",      F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|SIMM13(~0),   "1,!", 0, 0, v9 },   /* wrpr r1,%priv */
-{ "wrpr",      F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "1,i,!", 0, 0, v9 }, /* wrpr r1,i,%priv */
-{ "wrpr",      F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "i,1,!", F_ALIAS, 0, v9 }, /* wrpr i,r1,%priv */
-{ "wrpr",      F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RS1(~0),      "i,!", 0, 0, v9 },   /* wrpr i,%priv */
-
-{ "rdhpr",     F3(2, 0x29, 0),         F3(~2, ~0x29, ~0)|SIMM13(~0),   "$,d", 0, 0, v9 },   /* rdhpr %hpriv,r */
-{ "wrhpr",     F3(2, 0x33, 0),         F3(~2, ~0x33, ~0),              "1,2,%", 0, 0, v9 }, /* wrhpr r1,r2,%hpriv */
-{ "wrhpr",     F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|SIMM13(~0),   "1,%", 0, 0, v9 },   /* wrhpr r1,%hpriv */
-{ "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "1,i,%", 0, 0, v9 }, /* wrhpr r1,i,%hpriv */
-{ "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "i,1,%", F_ALIAS, 0, v9 }, /* wrhpr i,r1,%hpriv */
-{ "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RS1(~0),      "i,%", 0, 0, v9 },   /* wrhpr i,%hpriv */
-
-{ "mov",       F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", F_ALIAS, 0, v8 }, /* rd %asr1,r */
-{ "mov",       F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", F_ALIAS, 0, v6 }, /* rd %y,r */
-{ "mov",       F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", F_ALIAS, 0, v6notv9 }, /* rd %psr,r */
-{ "mov",       F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", F_ALIAS, 0, v6notv9 }, /* rd %wim,r */
-{ "mov",       F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", F_ALIAS, 0, v6notv9 }, /* rd %tbr,r */
-
-{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
-{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
-{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
-{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */
-{ "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
-{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
-{ "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
-{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
-{ "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
-{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
-
-{ "mov",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),       "2,d", 0, 0, v6 }, /* or %g0,rs2,d */
-{ "mov",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, 0, v6 }, /* or %g0,i,d        */
-{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),         "1,d", 0, 0, v6 }, /* or rs1,%g0,d   */
-{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),          "1,d", 0, 0, v6 }, /* or rs1,0,d */
-
-{ "or",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "1,i,d", 0, 0, v6 },
-{ "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,1,d", 0, 0, v6 },
-
-{ "bset",      F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "2,r", F_ALIAS, 0, v6 },        /* or rd,rs2,rd */
-{ "bset",      F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,r", F_ALIAS, 0, v6 },        /* or rd,i,rd */
+{ "orn",       F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "orn",       F3(2, 0x06, 1), F3(~2, ~0x06, ~1),              "1,i,d", 0, 0, 0, v6 },
+
+{ "tst",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),    "1", 0, 0, 0, v6 }, /* orcc rs1, %g0, %g0 */
+{ "tst",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, 0, v6 }, /* orcc %g0, rs2, %g0 */
+{ "tst",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),     "1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */
+
+
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI(~0),              "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|SIMM13(~0),           "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%asrX */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|ASI_RS2(~0),          "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%g0,%asrX */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", 0, 0, 0, v6 }, /* wr r,r,%y */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, 0, 0, v6 }, /* wr r,i,%y */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */
+{ "wr",        F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),     "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,0,%y */
+{ "wr",        F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),    "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,%g0,%y */
+{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", 0, 0, 0, v6notv9 }, /* wr r,r,%psr */
+{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", 0, 0, 0, v6notv9 }, /* wr r,i,%psr */
+{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */
+{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */
+{ "wr",        F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),     "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%psr */
+{ "wr",        F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),    "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%psr */
+{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", 0, 0, 0, v6notv9 }, /* wr r,r,%wim */
+{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", 0, 0, 0, v6notv9 }, /* wr r,i,%wim */
+{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */
+{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */
+{ "wr",        F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),     "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%wim */
+{ "wr",        F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),    "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%wim */
+{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", 0, 0, 0, v6notv9 }, /* wr r,r,%tbr */
+{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", 0, 0, 0, v6notv9 }, /* wr r,i,%tbr */
+{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
+{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */
+{ "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),     "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%tbr */
+{ "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),    "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
+
+{ "wr", F3(2, 0x30, 0)|RD(2),  F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),       "1,2,E", 0, 0, 0, v9 }, /* wr r,r,%ccr */
+{ "wr", F3(2, 0x30, 1)|RD(2),  F3(~2, ~0x30, ~1)|RD(~2),               "1,i,E", 0, 0, 0, v9 }, /* wr r,i,%ccr */
+{ "wr", F3(2, 0x30, 0)|RD(3),  F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),       "1,2,o", 0, 0, 0, v9 }, /* wr r,r,%asi */
+{ "wr", F3(2, 0x30, 1)|RD(3),  F3(~2, ~0x30, ~1)|RD(~3),               "1,i,o", 0, 0, 0, v9 }, /* wr r,i,%asi */
+{ "wr", F3(2, 0x30, 0)|RD(6),  F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),       "1,2,s", 0, 0, 0, v9 }, /* wr r,r,%fprs */
+{ "wr", F3(2, 0x30, 1)|RD(6),  F3(~2, ~0x30, ~1)|RD(~6),               "1,i,s", 0, 0, 0, v9 }, /* wr r,i,%fprs */
+{ "wr", F3(2, 0x30, 0)|RD(14),  F3(~2, ~0x30, ~0)|RD(~14),              "1,2,{", 0, 0, HWCAP2_SPARC5, v9b }, /* wr r,r,%mcdper */
+{ "wr", F3(2, 0x30, 1)|RD(14),  F3(~2, ~0x30, ~1)|RD(~14),              "1,i,{", 0, 0, HWCAP2_SPARC5, v9b }, /* wr r,i,%mcdper */
+
+{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%pcr */
+{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%pcr */
+{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%pic */
+{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%pic */
+{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%dcr */
+{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%dcr */
+{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%gsr */
+{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%gsr */
+{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%set_softint */
+{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%set_softint */
+{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%clear_softint */
+{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%clear_softint */
+{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%softint */
+{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%softint */
+{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),      "1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%tick_cmpr */
+{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23),              "1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%tick_cmpr */
+{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),      "1,2,_", HWCAP_VIS2, 0, 0, v9b }, /* wr r,r,%sys_tick */
+{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24),              "1,i,_", HWCAP_VIS2, 0, 0, v9b }, /* wr r,i,%sys_tick */
+{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),      "1,2,_", HWCAP_VIS2, 0, 0, v9b }, /* wr r,r,%sys_tick_cmpr */
+{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25),              "1,i,_", HWCAP_VIS2, 0, 0, v9b }, /* wr r,i,%sys_tick_cmpr */
+{ "wr", F3(2, 0x30, 0)|RD(26), F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0),      "1,2,_", 0, HWCAP_CBCOND, 0, v9b }, /* wr r,r,%cfr */
+{ "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26),              "1,i,_", 0, HWCAP_CBCOND, 0, v9b }, /* wr r,i,%cfr */
+{ "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0),      "1,2,_", 0, HWCAP_PAUSE, 0, v9b }, /* wr r,r,%pause */
+{ "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27),              "1,i,_", 0, HWCAP_PAUSE, 0, v9b }, /* wr r,i,%pause */
+{ "wr",    F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, 0, HWCAP2_MWAIT, v9b }, /* wr r,r,%mwait */
+{ "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28),              "1,i,_", 0, 0, HWCAP2_MWAIT, v9b }, /* wr r,i,%mwait */
+
+{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9b }, /* wr %g0,i,%pause */
+
+{ "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", 0, 0, 0, v8 }, /* rd %asrX,r */
+{ "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", 0, 0, 0, v6 }, /* rd %y,r */
+{ "rd",        F3(2, 0x29, 0),                 F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", 0, 0, 0, v6notv9 }, /* rd %psr,r */
+{ "rd",        F3(2, 0x2a, 0),                 F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", 0, 0, 0, v6notv9 }, /* rd %wim,r */
+{ "rd",        F3(2, 0x2b, 0),                 F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", 0, 0, 0, v6notv9 }, /* rd %tbr,r */
+
+{ "rd",        F3(2, 0x28, 0)|RS1(2),          F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),   "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(3),          F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0),   "o,d", 0, 0, 0, v9 }, /* rd %asi,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(4),          F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),   "W,d", 0, 0, 0, v9 }, /* rd %tick,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(5),          F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),   "P,d", 0, 0, 0, v9 }, /* rd %pc,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(6),          F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),   "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */
+{ "rd", F3(2, 0x28, 0)|RS1(14),         F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0),  "{,d", 0, 0, HWCAP2_SPARC5, v9b }, /* rd %mcdper,r */
+
+{ "rd",        F3(2, 0x28, 0)|RS1(16),         F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %pcr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(17),         F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %pic,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(18),         F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %dcr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(19),         F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %gsr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(22),         F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %softint,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(23),         F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),  "/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %tick_cmpr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(24),         F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),  "/,d", 0, HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(25),         F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),  "/,d", 0, HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(26),         F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0),  "/,d", 0, HWCAP_CBCOND, 0, v9b }, /* rd %cfr,r */
+{ "rd",        F3(2, 0x28, 0)|RS1(28),         F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0),  "/,d", 0, 0, HWCAP2_MWAIT, v9b }, /* rd %mwait,r */
+
+{ "rdpr",      F3(2, 0x2a, 0),         F3(~2, ~0x2a, ~0)|SIMM13(~0),   "?,d", 0, 0, 0, v9 },   /* rdpr %priv,r */
+{ "wrpr",      F3(2, 0x32, 0),         F3(~2, ~0x32, ~0),              "1,2,!", 0, 0, 0, v9 }, /* wrpr r1,r2,%priv */
+{ "wrpr",      F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|SIMM13(~0),   "1,!", 0, 0, 0, v9 },   /* wrpr r1,%priv */
+{ "wrpr",      F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "1,i,!", 0, 0, 0, v9 }, /* wrpr r1,i,%priv */
+{ "wrpr",      F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "i,1,!", F_ALIAS, 0, 0, v9 }, /* wrpr i,r1,%priv */
+{ "wrpr",      F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RS1(~0),      "i,!", 0, 0, 0, v9 },   /* wrpr i,%priv */
+
+{ "rdhpr",     F3(2, 0x29, 0),         F3(~2, ~0x29, ~0)|SIMM13(~0),   "$,d", 0, 0, 0, v9 },   /* rdhpr %hpriv,r */
+{ "wrhpr",     F3(2, 0x33, 0),         F3(~2, ~0x33, ~0),              "1,2,%", 0, 0, 0, v9 }, /* wrhpr r1,r2,%hpriv */
+{ "wrhpr",     F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|SIMM13(~0),   "1,%", 0, 0, 0, v9 },   /* wrhpr r1,%hpriv */
+{ "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "1,i,%", 0, 0, 0, v9 }, /* wrhpr r1,i,%hpriv */
+{ "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "i,1,%", F_ALIAS, 0, 0, v9 }, /* wrhpr i,r1,%hpriv */
+{ "wrhpr",     F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RS1(~0),      "i,%", 0, 0, 0, v9 },   /* wrhpr i,%hpriv */
+
+{ "mov",       F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", F_ALIAS, 0, 0, v8 }, /* rd %asr1,r */
+{ "mov",       F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", F_ALIAS, 0, 0, v6 }, /* rd %y,r */
+{ "mov",       F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),    "p,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %psr,r */
+{ "mov",       F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),    "w,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %wim,r */
+{ "mov",       F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),    "t,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %tbr,r */
+
+{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),       "2,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */
+{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0,               "i,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */
+{ "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */
+{ "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,         "i,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */
+{ "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */
+{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,         "i,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */
+{ "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */
+{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,         "i,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */
+{ "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
+{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,         "i,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */
+
+{ "mov",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),       "2,d", 0, 0, 0, v6 }, /* or %g0,rs2,d */
+{ "mov",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, 0, 0, v6 }, /* or %g0,i,d     */
+{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),         "1,d", 0, 0, 0, v6 }, /* or rs1,%g0,d   */
+{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),          "1,d", 0, 0, 0, v6 }, /* or rs1,0,d */
+
+{ "or",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "or",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,1,d", 0, 0, 0, v6 },
+
+{ "bset",      F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),      "2,r", F_ALIAS, 0, 0, v6 },     /* or rd,rs2,rd */
+{ "bset",      F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,r", F_ALIAS, 0, 0, v6 },     /* or rd,i,rd */
 
 /* This is not a commutative instruction.  */
-{ "andn",      F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "andn",      F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "1,i,d", 0, 0, v6 },
+{ "andn",      F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "andn",      F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "1,i,d", 0, 0, 0, v6 },
 
 /* This is not a commutative instruction.  */
-{ "andncc",    F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "andncc",    F3(2, 0x15, 1), F3(~2, ~0x15, ~1),              "1,i,d", 0, 0, v6 },
-
-{ "bclr",      F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "2,r", F_ALIAS, 0, v6 },        /* andn rd,rs2,rd */
-{ "bclr",      F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "i,r", F_ALIAS, 0, v6 },        /* andn rd,i,rd */
-
-{ "cmp",       F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),        "1,2", 0, 0, v6 },      /* subcc rs1,rs2,%g0 */
-{ "cmp",       F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,                "1,i", 0, 0, v6 },      /* subcc rs1,i,%g0 */
-
-{ "sub",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "sub",       F3(2, 0x04, 1), F3(~2, ~0x04, ~1),              "1,i,d", 0, 0, v6 },
-
-{ "subcc",     F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "subcc",     F3(2, 0x14, 1), F3(~2, ~0x14, ~1),              "1,i,d", 0, 0, v6 },
-
-{ "subx",      F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", 0, 0, v6notv9 },
-{ "subx",      F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, 0, v6notv9 },
-{ "subc",      F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "subc",      F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, 0, v9 },
-
-{ "subxcc",    F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", 0, 0, v6notv9 },
-{ "subxcc",    F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, 0, v6notv9 },
-{ "subccc",    F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "subccc",    F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, 0, v9 },
-
-{ "and",       F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "and",       F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "1,i,d", 0, 0, v6 },
-{ "and",       F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "i,1,d", 0, 0, v6 },
-
-{ "andcc",     F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "andcc",     F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "1,i,d", 0, 0, v6 },
-{ "andcc",     F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "i,1,d", 0, 0, v6 },
-
-{ "dec",       F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },   /* sub rd,1,rd */
-{ "dec",       F3(2, 0x04, 1),             F3(~2, ~0x04, ~1),                 "i,r", F_ALIAS, 0, v8 }, /* sub rd,imm,rd */
-{ "deccc",     F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },   /* subcc rd,1,rd */
-{ "deccc",     F3(2, 0x14, 1),             F3(~2, ~0x14, ~1),                 "i,r", F_ALIAS, 0, v8 }, /* subcc rd,imm,rd */
-{ "inc",       F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },   /* add rd,1,rd */
-{ "inc",       F3(2, 0x00, 1),             F3(~2, ~0x00, ~1),                 "i,r", F_ALIAS, 0, v8 }, /* add rd,imm,rd */
-{ "inccc",     F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },   /* addcc rd,1,rd */
-{ "inccc",     F3(2, 0x10, 1),             F3(~2, ~0x10, ~1),                 "i,r", F_ALIAS, 0, v8 }, /* addcc rd,imm,rd */
-
-{ "btst",      F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, v6 },       /* andcc rs1,rs2,%g0 */
-{ "btst",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, v6 },       /* andcc rs1,i,%g0 */
-
-{ "neg",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, v6 }, /* sub %g0,rs2,rd */
-{ "neg",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, v6 }, /* sub %g0,rd,rd */
-
-{ "add",       F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "add",       F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "1,i,d", 0, 0, v6 },
-{ "add",       F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "i,1,d", 0, 0, v6 },
-{ "addcc",     F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "addcc",     F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "1,i,d", 0, 0, v6 },
-{ "addcc",     F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "i,1,d", 0, 0, v6 },
-
-{ "addx",      F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", 0, 0, v6notv9 },
-{ "addx",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, 0, v6notv9 },
-{ "addx",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, 0, v6notv9 },
-{ "addc",      F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "addc",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, 0, v9 },
-{ "addc",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, 0, v9 },
-
-{ "addxcc",    F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", 0, 0, v6notv9 },
-{ "addxcc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, 0, v6notv9 },
-{ "addxcc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, 0, v6notv9 },
-{ "addccc",    F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "addccc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, 0, v9 },
-{ "addccc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, 0, v9 },
-
-{ "smul",      F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, v8 },
-{ "smul",      F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "1,i,d", 0, HWCAP_MUL32, v8 },
-{ "smul",      F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "i,1,d", 0, HWCAP_MUL32, v8 },
-{ "smulcc",    F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, v8 },
-{ "smulcc",    F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "1,i,d", 0, HWCAP_MUL32, v8 },
-{ "smulcc",    F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "i,1,d", 0, HWCAP_MUL32, v8 },
-{ "umul",      F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, v8 },
-{ "umul",      F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "1,i,d", 0, HWCAP_MUL32, v8 },
-{ "umul",      F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "i,1,d", 0, HWCAP_MUL32, v8 },
-{ "umulcc",    F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, v8 },
-{ "umulcc",    F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "1,i,d", 0, HWCAP_MUL32, v8 },
-{ "umulcc",    F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "i,1,d", 0, HWCAP_MUL32, v8 },
-{ "sdiv",      F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, v8 },
-{ "sdiv",      F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "1,i,d", 0, HWCAP_DIV32, v8 },
-{ "sdiv",      F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "i,1,d", 0, HWCAP_DIV32, v8 },
-{ "sdivcc",    F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, v8 },
-{ "sdivcc",    F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "1,i,d", 0, HWCAP_DIV32, v8 },
-{ "sdivcc",    F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "i,1,d", 0, HWCAP_DIV32, v8 },
-{ "udiv",      F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, v8 },
-{ "udiv",      F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "1,i,d", 0, HWCAP_DIV32, v8 },
-{ "udiv",      F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "i,1,d", 0, HWCAP_DIV32, v8 },
-{ "udivcc",    F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, v8 },
-{ "udivcc",    F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "1,i,d", 0, HWCAP_DIV32, v8 },
-{ "udivcc",    F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "i,1,d", 0, HWCAP_DIV32, v8 },
-
-{ "mulx",      F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "mulx",      F3(2, 0x09, 1), F3(~2, ~0x09, ~1),              "1,i,d", 0, 0, v9 },
-{ "sdivx",     F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "sdivx",     F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, 0, v9 },
-{ "udivx",     F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0),      "1,2,d", 0, 0, v9 },
-{ "udivx",     F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1),              "1,i,d", 0, 0, v9 },
-
-{ "call",      F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, v6 },
-{ "call",      F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, v6 },
-
-{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%o7 */
-{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2,#", F_JSR|F_DELAYED, 0, v6 },
-{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%o7 */
-{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, v6 },
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%o7 */
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i,#", F_JSR|F_DELAYED, 0, v6 },
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%o7 */
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1,#", F_JSR|F_DELAYED, 0, v6 },
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%o7 */
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i,#", F_JSR|F_DELAYED, 0, v6 },
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%o7 */
-{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1,#", F_JSR|F_DELAYED, 0, v6 },
-
-{ "chkpt",     F2(0, 1)|CONDA|ANNUL|(1<<20), F2(~0, ~1)|((~CONDA)&COND(~0)), "G", 0, HWCAP_TRANS, v9b },
+{ "andncc",    F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "andncc",    F3(2, 0x15, 1), F3(~2, ~0x15, ~1),              "1,i,d", 0, 0, 0, v6 },
+
+{ "bclr",      F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),      "2,r", F_ALIAS, 0, 0, v6 },     /* andn rd,rs2,rd */
+{ "bclr",      F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "i,r", F_ALIAS, 0, 0, v6 },     /* andn rd,i,rd */
+
+{ "cmp",       F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),        "1,2", 0, 0, 0, v6 },   /* subcc rs1,rs2,%g0 */
+{ "cmp",       F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,                "1,i", 0, 0, 0, v6 },   /* subcc rs1,i,%g0 */
+
+{ "sub",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "sub",       F3(2, 0x04, 1), F3(~2, ~0x04, ~1),              "1,i,d", 0, 0, 0, v6 },
+
+{ "subcc",     F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "subcc",     F3(2, 0x14, 1), F3(~2, ~0x14, ~1),              "1,i,d", 0, 0, 0, v6 },
+
+{ "subx",      F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6notv9 },
+{ "subx",      F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, 0, 0, v6notv9 },
+{ "subc",      F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "subc",      F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, 0, 0, v9 },
+
+{ "subxcc",    F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6notv9 },
+{ "subxcc",    F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, 0, 0, v6notv9 },
+{ "subccc",    F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "subccc",    F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, 0, 0, v9 },
+
+{ "and",       F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "and",       F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "and",       F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "i,1,d", 0, 0, 0, v6 },
+
+{ "andcc",     F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "andcc",     F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "andcc",     F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "i,1,d", 0, 0, 0, v6 },
+
+{ "dec",       F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 },        /* sub rd,1,rd */
+{ "dec",       F3(2, 0x04, 1),             F3(~2, ~0x04, ~1),                 "i,r", F_ALIAS, 0, 0, v8 },      /* sub rd,imm,rd */
+{ "deccc",     F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 },        /* subcc rd,1,rd */
+{ "deccc",     F3(2, 0x14, 1),             F3(~2, ~0x14, ~1),                 "i,r", F_ALIAS, 0, 0, v8 },      /* subcc rd,imm,rd */
+{ "inc",       F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 },        /* add rd,1,rd */
+{ "inc",       F3(2, 0x00, 1),             F3(~2, ~0x00, ~1),                 "i,r", F_ALIAS, 0, 0, v8 },      /* add rd,imm,rd */
+{ "inccc",     F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 },        /* addcc rd,1,rd */
+{ "inccc",     F3(2, 0x10, 1),             F3(~2, ~0x10, ~1),                 "i,r", F_ALIAS, 0, 0, v8 },      /* addcc rd,imm,rd */
+
+{ "btst",      F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, 0, v6 },    /* andcc rs1,rs2,%g0 */
+{ "btst",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, 0, v6 },    /* andcc rs1,i,%g0 */
+
+{ "neg",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, 0, v6 }, /* sub %g0,rs2,rd */
+{ "neg",       F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, 0, v6 }, /* sub %g0,rd,rd */
+
+{ "add",       F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "add",       F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "add",       F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "i,1,d", 0, 0, 0, v6 },
+{ "addcc",     F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "addcc",     F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "addcc",     F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "i,1,d", 0, 0, 0, v6 },
+
+{ "addx",      F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6notv9 },
+{ "addx",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, 0, 0, v6notv9 },
+{ "addx",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, 0, 0, v6notv9 },
+{ "addc",      F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "addc",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, 0, 0, v9 },
+{ "addc",      F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, 0, 0, v9 },
+
+{ "addxcc",    F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6notv9 },
+{ "addxcc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, 0, 0, v6notv9 },
+{ "addxcc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, 0, 0, v6notv9 },
+{ "addccc",    F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "addccc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, 0, 0, v9 },
+{ "addccc",    F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, 0, 0, v9 },
+
+{ "smul",      F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, 0, v8 },
+{ "smul",      F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "1,i,d", 0, HWCAP_MUL32, 0, v8 },
+{ "smul",      F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "i,1,d", 0, HWCAP_MUL32, 0, v8 },
+{ "smulcc",    F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, 0, v8 },
+{ "smulcc",    F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "1,i,d", 0, HWCAP_MUL32, 0, v8 },
+{ "smulcc",    F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "i,1,d", 0, HWCAP_MUL32, 0, v8 },
+{ "umul",      F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, 0, v8 },
+{ "umul",      F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "1,i,d", 0, HWCAP_MUL32, 0, v8 },
+{ "umul",      F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "i,1,d", 0, HWCAP_MUL32, 0, v8 },
+{ "umulcc",    F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_MUL32, 0, v8 },
+{ "umulcc",    F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "1,i,d", 0, HWCAP_MUL32, 0, v8 },
+{ "umulcc",    F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "i,1,d", 0, HWCAP_MUL32, 0, v8 },
+{ "sdiv",      F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, 0, v8 },
+{ "sdiv",      F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "1,i,d", 0, HWCAP_DIV32, 0, v8 },
+{ "sdiv",      F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "i,1,d", 0, HWCAP_DIV32, 0, v8 },
+{ "sdivcc",    F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, 0, v8 },
+{ "sdivcc",    F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "1,i,d", 0, HWCAP_DIV32, 0, v8 },
+{ "sdivcc",    F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "i,1,d", 0, HWCAP_DIV32, 0, v8 },
+{ "udiv",      F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, 0, v8 },
+{ "udiv",      F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "1,i,d", 0, HWCAP_DIV32, 0, v8 },
+{ "udiv",      F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "i,1,d", 0, HWCAP_DIV32, 0, v8 },
+{ "udivcc",    F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),      "1,2,d", 0, HWCAP_DIV32, 0, v8 },
+{ "udivcc",    F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "1,i,d", 0, HWCAP_DIV32, 0, v8 },
+{ "udivcc",    F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "i,1,d", 0, HWCAP_DIV32, 0, v8 },
+
+{ "mulx",      F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "mulx",      F3(2, 0x09, 1), F3(~2, ~0x09, ~1),              "1,i,d", 0, 0, 0, v9 },
+{ "sdivx",     F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "sdivx",     F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, 0, 0, v9 },
+{ "udivx",     F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v9 },
+{ "udivx",     F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1),              "1,i,d", 0, 0, 0, v9 },
+
+{ "call",      F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "call",      F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, 0, v6 },
+
+{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%o7 */
+{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),     "1+2,#", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%o7 */
+{ "call",      F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%o7 */
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i,#", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%o7 */
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1,#", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%o7 */
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i,#", F_JSR|F_DELAYED, 0, 0, v6 },
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%o7 */
+{ "call",      F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),  "1,#", F_JSR|F_DELAYED, 0, 0, v6 },
 
 /* Conditional instructions.
 
@@ -1128,38 +1130,38 @@ const struct sparc_opcode sparc_opcodes[] = {
 
 /* Define branches -- one annulled, one without, etc. */
 #define br(opcode, mask, lose, flags) \
- { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), 0, v6 }, \
- { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), 0, v6 }
+ { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), 0, 0, v6 }, \
+ { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), 0, 0, v6 }
 
 #define brx(opcode, mask, lose, flags) /* v9 */ \
- { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G",      (flags), 0, v9 }, \
- { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G",   (flags), 0, v9 }, \
- { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G",   (flags), 0, v9 }, \
- { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, v9 }, \
- { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G",   (flags), 0, v9 }, \
- { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, v9 }, \
- { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G",      (flags), 0, v9 }, \
- { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G",   (flags), 0, v9 }, \
- { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G",   (flags), 0, v9 }, \
- { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, v9 }, \
- { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G",   (flags), 0, v9 }, \
- { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, v9 }
+ { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G",      (flags), 0, 0, v9 }, \
+ { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G",   (flags), 0, 0, v9 }, \
+ { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G",   (flags), 0, 0, v9 }, \
+ { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, 0, v9 }, \
+ { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G",   (flags), 0, 0, v9 }, \
+ { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G",      (flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G",   (flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G",   (flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, 0, v9 }, \
+ { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G",   (flags), 0, 0, v9 }, \
+ { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, 0, v9 }
 
 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
 #define tr(opcode, mask, lose, flags) \
- { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0,        "Z,i",   (flags), 0, v9 }, /* %g0 + imm */ \
- { opcode, (mask)|(2<<11)|IMMED, (lose),       "Z,1+i", (flags), 0, v9 }, /* rs1 + imm */ \
- { opcode, (mask)|(2<<11), IMMED|(lose),       "Z,1+2", (flags), 0, v9 }, /* rs1 + rs2 */ \
- { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0,        "Z,1",   (flags), 0, v9 }, /* rs1 + %g0 */ \
- { opcode, (mask)|IMMED, (lose)|RS1_G0,        "z,i",   (flags)|F_ALIAS, 0, v9 }, /* %g0 + imm */ \
- { opcode, (mask)|IMMED, (lose),       "z,1+i", (flags)|F_ALIAS, 0, v9 }, /* rs1 + imm */ \
- { opcode, (mask), IMMED|(lose),       "z,1+2", (flags)|F_ALIAS, 0, v9 }, /* rs1 + rs2 */ \
- { opcode, (mask), IMMED|(lose)|RS2_G0,        "z,1",   (flags)|F_ALIAS, 0, v9 }, /* rs1 + %g0 */ \
- { opcode, (mask)|IMMED, (lose)|RS1_G0,                "i",     (flags), 0, v6 }, /* %g0 + imm */ \
- { opcode, (mask)|IMMED, (lose),               "1+i",   (flags), 0, v6 }, /* rs1 + imm */ \
- { opcode, (mask)|IMMED, (lose),               "i+1",   (flags), 0, v6 }, /* imm + rs1 */ \
- { opcode, (mask), IMMED|(lose),               "1+2",   (flags), 0, v6 }, /* rs1 + rs2 */ \
- { opcode, (mask), IMMED|(lose)|RS2_G0,                "1",     (flags), 0, v6 } /* rs1 + %g0 */
+ { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0,        "Z,i",   (flags), 0, 0, v9 }, /* %g0 + imm */ \
+ { opcode, (mask)|(2<<11)|IMMED, (lose),       "Z,1+i", (flags), 0, 0, v9 }, /* rs1 + imm */ \
+ { opcode, (mask)|(2<<11), IMMED|(lose),       "Z,1+2", (flags), 0, 0, v9 }, /* rs1 + rs2 */ \
+ { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0,        "Z,1",   (flags), 0, 0, v9 }, /* rs1 + %g0 */ \
+ { opcode, (mask)|IMMED, (lose)|RS1_G0,        "z,i",   (flags)|F_ALIAS, 0, 0, v9 }, /* %g0 + imm */ \
+ { opcode, (mask)|IMMED, (lose),       "z,1+i", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + imm */ \
+ { opcode, (mask), IMMED|(lose),       "z,1+2", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + rs2 */ \
+ { opcode, (mask), IMMED|(lose)|RS2_G0,        "z,1",   (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + %g0 */ \
+ { opcode, (mask)|IMMED, (lose)|RS1_G0,                "i",     (flags), 0, 0, v6 }, /* %g0 + imm */ \
+ { opcode, (mask)|IMMED, (lose),               "1+i",   (flags), 0, 0, v6 }, /* rs1 + imm */ \
+ { opcode, (mask)|IMMED, (lose),               "i+1",   (flags), 0, 0, v6 }, /* imm + rs1 */ \
+ { opcode, (mask), IMMED|(lose),               "1+2",   (flags), 0, 0, v6 }, /* rs1 + rs2 */ \
+ { opcode, (mask), IMMED|(lose)|RS2_G0,                "1",     (flags), 0, 0, v6 } /* rs1 + %g0 */
 
 /* v9: We must put `brx' before `br', to ensure that we never match something
    v9: against an expression unless it is an expression.  Otherwise, we end
@@ -1208,12 +1210,12 @@ cond ("bz",     "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
 #undef tr
 
 #define brr(opcode, mask, lose, flags) /* v9 */ \
- { opcode, (mask)|BPRED, ANNUL|(lose), "1,k",      F_DELAYED|(flags), 0, v9 }, \
- { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k",   F_DELAYED|(flags), 0, v9 }, \
- { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k",   F_DELAYED|(flags), 0, v9 }, \
- { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, v9 }, \
- { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k",   F_DELAYED|(flags), 0, v9 }, \
- { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, v9 }
+ { opcode, (mask)|BPRED, ANNUL|(lose), "1,k",      F_DELAYED|(flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k",   F_DELAYED|(flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k",   F_DELAYED|(flags), 0, 0, v9 }, \
+ { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \
+ { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k",   F_DELAYED|(flags), 0, 0, v9 }, \
+ { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, 0, v9 }
 
 #define condr(bop, mask, flags) /* v9 */ \
   brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
@@ -1227,13 +1229,13 @@ cond ("bz",     "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
 
 #define cbcond(cop, cmask, flgs) \
   { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
-    "1,2,=", flgs, HWCAP_CBCOND, v9}, \
+    "1,2,=", flgs, HWCAP_CBCOND, 0, v9}, \
   { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
-    "1,X,=", flgs, HWCAP_CBCOND, v9}, \
+    "1,X,=", flgs, HWCAP_CBCOND, 0, v9}, \
   { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
-    "1,2,=", flgs, HWCAP_CBCOND, v9}, \
+    "1,2,=", flgs, HWCAP_CBCOND, 0, v9}, \
   { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
-    "1,X,=", flgs, HWCAP_CBCOND, v9},
+    "1,X,=", flgs, HWCAP_CBCOND, 0, v9},
 
 cbcond("be",   0x09, F_CONDBR)
 cbcond("bz",   0x09, F_CONDBR|F_ALIAS)
@@ -1259,15 +1261,15 @@ cbcond("bvc",  0x1f, F_CONDBR)
 #undef brr /* v9 */
 
 #define movr(opcode, mask, flags) /* v9 */ \
- { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, v9 }, \
- { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, v9 }
+ { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, 0, v9 }, \
+ { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, 0, v9 }
 
 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
- { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, v9 }
+ { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, 0, v9 }
 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
- { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, v9 }
+ { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, 0, v9 }
 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
- { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, v9 }
+ { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, 0, v9 }
 
 #define fmovrs(mop, mask, flags) /* v9 */ \
   fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
@@ -1317,20 +1319,20 @@ cbcond("bvc",  0x1f, F_CONDBR)
 #undef fmrr /* v9 */
 
 #define movicc(opcode, cond, flags) /* v9 */ \
-  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11),     "Z,2,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11),     "Z,I,d", flags, 0, v9 }
+  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11),     "Z,2,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11),     "Z,I,d", flags, 0, 0, v9 }
 
 #define movfcc(opcode, fcond, flags) /* v9 */ \
-  { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, v9 }, \
-  { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, v9 }
+  { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, 0, v9 }, \
+  { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, 0, v9 }
 
 #define movcc(opcode, cond, fcond, flags) /* v9 */ \
   movfcc (opcode, fcond, flags), /* v9 */ \
@@ -1374,23 +1376,23 @@ cbcond("bvc",  0x1f, F_CONDBR)
 #define FM_QF 3                /* v9 */
 
 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
-{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags, 0, v9 }
+{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags, 0, 0, v9 }
 
 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
-{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, v9 }
+{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, 0, v9 }
 
 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
-{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags | F_FLOAT, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags | F_FLOAT, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, v9 }, \
-{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, v9 }
+{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags | F_FLOAT, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags | F_FLOAT, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, 0, v9 }, \
+{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, 0, v9 }
 
 #define fmovicc(suffix, cond, flags) /* v9 */ \
 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags),           \
@@ -1448,40 +1450,40 @@ fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
 
 /* Coprocessor branches.  */
 #define CBR(opcode, mask, lose, flags, arch) \
- { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED, 0, arch }, \
- { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, arch }
+ { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED, 0, 0, arch }, \
+ { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, 0, arch }
 
 /* Floating point branches.  */
 #define FBR(opcode, mask, lose, flags) \
- { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED | F_FBR, 0, v6 }, \
- { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, v6 }
+ { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED | F_FBR, 0, 0, v6 }, \
+ { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, 0, v6 }
 
 /* V9 extended floating point branches.  */
 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
- { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
- { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, v9 }
+ { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",      flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",      flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",      flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",      flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",   flags|F_DELAYED|F_FBR, 0, 0, v9 }, \
+ { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }
 
 /* v9: We must put `FBRX' before `FBR', to ensure that we never match
    v9: something against an expression unless it is an expression.  Otherwise,
@@ -1529,173 +1531,173 @@ CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
 #undef FBR
 #undef FBRX    /* v9 */
 
-{ "jmp",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%g0 */
-{ "jmp",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%g0 */
-{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%g0 */
-{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%g0 */
-{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%g0 */
-{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%g0 */
+{ "jmp",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%g0 */
+{ "jmp",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%g0 */
+{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%g0 */
+{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%g0 */
+{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%g0 */
+{ "jmp",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%g0 */
 
-{ "nop",       F2(0, 4), 0xfeffffff, "", 0, 0, v6 }, /* sethi 0, %g0 */
+{ "nop",       F2(0, 4), 0xfeffffff, "", 0, 0, 0, v6 }, /* sethi 0, %g0 */
 
-{ "set",       F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v6 },
-{ "setuw",     F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 },
-{ "setsw",     F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 },
-{ "setx",      F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, v9 },
+{ "set",       F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v6 },
+{ "setuw",     F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 },
+{ "setsw",     F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 },
+{ "setx",      F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, 0, v9 },
 
-{ "sethi",     F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, v6 },
+{ "sethi",     F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, 0, v6 },
 
-{ "taddcc",    F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "taddcc",    F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "1,i,d", 0, 0, v6 },
-{ "taddcc",    F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "i,1,d", 0, 0, v6 },
-{ "taddcctv",  F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "taddcctv",  F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "1,i,d", 0, 0, v6 },
-{ "taddcctv",  F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "i,1,d", 0, 0, v6 },
+{ "taddcc",    F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "taddcc",    F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "taddcc",    F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "i,1,d", 0, 0, 0, v6 },
+{ "taddcctv",  F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "taddcctv",  F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "taddcctv",  F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "i,1,d", 0, 0, 0, v6 },
 
-{ "tsubcc",    F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "tsubcc",    F3(2, 0x21, 1), F3(~2, ~0x21, ~1),              "1,i,d", 0, 0, v6 },
-{ "tsubcctv",  F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "tsubcctv",  F3(2, 0x23, 1), F3(~2, ~0x23, ~1),              "1,i,d", 0, 0, v6 },
+{ "tsubcc",    F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "tsubcc",    F3(2, 0x21, 1), F3(~2, ~0x21, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "tsubcctv",  F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "tsubcctv",  F3(2, 0x23, 1), F3(~2, ~0x23, ~1),              "1,i,d", 0, 0, 0, v6 },
 
-{ "unimp",     F2(0x0, 0x0), 0xffc00000, "n", 0, 0, v6notv9 },
-{ "illtrap",   F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, v9 },
+{ "unimp",     F2(0x0, 0x0), 0xffc00000, "n", 0, 0, 0, v6notv9 },
+{ "illtrap",   F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, 0, v9 },
 
 /* This *is* a commutative instruction.  */
-{ "xnor",      F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "xnor",      F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "1,i,d", 0, 0, v6 },
-{ "xnor",      F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "i,1,d", 0, 0, v6 },
+{ "xnor",      F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "xnor",      F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "xnor",      F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "i,1,d", 0, 0, 0, v6 },
 /* This *is* a commutative instruction.  */
-{ "xnorcc",    F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "xnorcc",    F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "1,i,d", 0, 0, v6 },
-{ "xnorcc",    F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "i,1,d", 0, 0, v6 },
-{ "xor",       F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "xor",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "1,i,d", 0, 0, v6 },
-{ "xor",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,1,d", 0, 0, v6 },
-{ "xorcc",     F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),      "1,2,d", 0, 0, v6 },
-{ "xorcc",     F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "1,i,d", 0, 0, v6 },
-{ "xorcc",     F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "i,1,d", 0, 0, v6 },
-
-{ "not",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, v6 }, /* xnor rs1,%0,rd */
-{ "not",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, v6 }, /* xnor rd,%0,rd */
-
-{ "btog",      F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "2,r", F_ALIAS, 0, v6 }, /* xor rd,rs2,rd */
-{ "btog",      F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,r", F_ALIAS, 0, v6 }, /* xor rd,i,rd */
+{ "xnorcc",    F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "xnorcc",    F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "xnorcc",    F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "i,1,d", 0, 0, 0, v6 },
+{ "xor",       F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "xor",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "xor",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,1,d", 0, 0, 0, v6 },
+{ "xorcc",     F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
+{ "xorcc",     F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "1,i,d", 0, 0, 0, v6 },
+{ "xorcc",     F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "i,1,d", 0, 0, 0, v6 },
+
+{ "not",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, 0, v6 }, /* xnor rs1,%0,rd */
+{ "not",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, 0, v6 }, /* xnor rd,%0,rd */
+
+{ "btog",      F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),      "2,r", F_ALIAS, 0, 0, v6 }, /* xor rd,rs2,rd */
+{ "btog",      F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,r", F_ALIAS, 0, 0, v6 }, /* xor rd,i,rd */
 
 /* FPop1 and FPop2 are not instructions.  Don't accept them.  */
 
-{ "fdtoi",     F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, v6 },
-{ "fstoi",     F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
-{ "fqtoi",     F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, v8 },
-
-{ "fdtox",     F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
-{ "fstox",     F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, v9 },
-{ "fqtox",     F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, v9 },
-
-{ "fitod",     F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, v6 },
-{ "fitos",     F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
-{ "fitoq",     F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, v8 },
-
-{ "fxtod",     F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
-{ "fxtos",     F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, v9 },
-{ "fxtoq",     F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, v9 },
-
-{ "fdtoq",     F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, v8 },
-{ "fdtos",     F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, v6 },
-{ "fqtod",     F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, v8 },
-{ "fqtos",     F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, v8 },
-{ "fstod",     F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, v6 },
-{ "fstoq",     F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, v8 },
-
-{ "fdivd",     F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, v6 },
-{ "fdivq",     F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, v8 },
-{ "fdivx",     F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fdivs",     F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, v6 },
-{ "fmuld",     F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, v6 },
-{ "fmulq",     F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, v8 },
-{ "fmulx",     F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fmuls",     F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, v6 },
-
-{ "fdmulq",    F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, v8 },
-{ "fdmulx",    F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fsmuld",    F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, v8 },
-
-{ "fsqrtd",    F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, v7 },
-{ "fsqrtq",    F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, v8 },
-{ "fsqrtx",    F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fsqrts",    F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, v7 },
-
-{ "fabsd",     F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
-{ "fabsq",     F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
-{ "fabsx",     F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fabss",     F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
-{ "fmovd",     F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
-{ "fmovq",     F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
-{ "fmovx",     F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fmovs",     F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
-{ "fnegd",     F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
-{ "fnegq",     F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
-{ "fnegx",     F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fnegs",     F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
-
-{ "faddd",     F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, v6 },
-{ "faddq",     F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, v8 },
-{ "faddx",     F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fadds",     F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, v6 },
-{ "fsubd",     F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, v6 },
-{ "fsubq",     F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, v8 },
-{ "fsubx",     F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fsubs",     F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, v6 },
+{ "fdtoi",     F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 },
+{ "fstoi",     F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fqtoi",     F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 },
+
+{ "fdtox",     F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
+{ "fstox",     F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, 0, v9 },
+{ "fqtox",     F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, 0, v9 },
+
+{ "fitod",     F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 },
+{ "fitos",     F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fitoq",     F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 },
+
+{ "fxtod",     F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
+{ "fxtos",     F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, 0, v9 },
+{ "fxtoq",     F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, 0, v9 },
+
+{ "fdtoq",     F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, 0, v8 },
+{ "fdtos",     F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 },
+{ "fqtod",     F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, 0, v8 },
+{ "fqtos",     F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 },
+{ "fstod",     F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 },
+{ "fstoq",     F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 },
+
+{ "fdivd",     F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, 0, v6 },
+{ "fdivq",     F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, 0, v8 },
+{ "fdivx",     F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fdivs",     F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, 0, v6 },
+{ "fmuld",     F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, 0, v6 },
+{ "fmulq",     F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, 0, v8 },
+{ "fmulx",     F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fmuls",     F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, 0, v6 },
+
+{ "fdmulq",    F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, 0, v8 },
+{ "fdmulx",    F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fsmuld",    F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, 0, v8 },
+
+{ "fsqrtd",    F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v7 },
+{ "fsqrtq",    F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v8 },
+{ "fsqrtx",    F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fsqrts",    F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, 0, v7 },
+
+{ "fabsd",     F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
+{ "fabsq",     F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
+{ "fabsx",     F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fabss",     F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fmovd",     F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
+{ "fmovq",     F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
+{ "fmovx",     F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fmovs",     F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+{ "fnegd",     F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 },
+{ "fnegq",     F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 },
+{ "fnegx",     F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fnegs",     F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 },
+
+{ "faddd",     F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, 0, v6 },
+{ "faddq",     F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, 0, v8 },
+{ "faddx",     F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fadds",     F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, 0, v6 },
+{ "fsubd",     F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, 0, v6 },
+{ "fsubq",     F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, 0, v8 },
+{ "fsubx",     F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fsubs",     F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, 0, v6 },
 
 #define CMPFCC(x)      (((x)&0x3)<<25)
 
-{ "fcmpd",               F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   F_FLOAT, 0, v6 },
-{ "fcmpd",     CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052),        "6,v,B", F_FLOAT, 0, v9 },
-{ "fcmpd",     CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052),        "7,v,B", F_FLOAT, 0, v9 },
-{ "fcmpd",     CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052),        "8,v,B", F_FLOAT, 0, v9 },
-{ "fcmpd",     CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052),        "9,v,B", F_FLOAT, 0, v9 },
-{ "fcmped",              F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   F_FLOAT, 0, v6 },
-{ "fcmped",    CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056),        "6,v,B", F_FLOAT, 0, v9 },
-{ "fcmped",    CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056),        "7,v,B", F_FLOAT, 0, v9 },
-{ "fcmped",    CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056),        "8,v,B", F_FLOAT, 0, v9 },
-{ "fcmped",    CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056),        "9,v,B", F_FLOAT, 0, v9 },
-{ "fcmpq",               F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT, 0, v8 },
-{ "fcmpq",     CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),        "6,V,R", F_FLOAT, 0, v9 },
-{ "fcmpq",     CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT, 0, v9 },
-{ "fcmpq",     CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT, 0, v9 },
-{ "fcmpq",     CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT, 0, v9 },
-{ "fcmpeq",              F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT, 0, v8 },
-{ "fcmpeq",    CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),        "6,V,R", F_FLOAT, 0, v9 },
-{ "fcmpeq",    CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT, 0, v9 },
-{ "fcmpeq",    CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT, 0, v9 },
-{ "fcmpeq",    CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT, 0, v9 },
-{ "fcmpx",               F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fcmpx",     CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),        "6,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpx",     CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpx",     CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpx",     CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpex",              F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, 0, v8 },
-{ "fcmpex",    CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),        "6,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpex",    CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpex",    CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmpex",    CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT|F_ALIAS, 0, v9 },
-{ "fcmps",               F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   F_FLOAT, 0, v6 },
-{ "fcmps",     CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051),        "6,e,f", F_FLOAT, 0, v9 },
-{ "fcmps",     CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051),        "7,e,f", F_FLOAT, 0, v9 },
-{ "fcmps",     CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051),        "8,e,f", F_FLOAT, 0, v9 },
-{ "fcmps",     CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051),        "9,e,f", F_FLOAT, 0, v9 },
-{ "fcmpes",              F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   F_FLOAT, 0, v6 },
-{ "fcmpes",    CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055),        "6,e,f", F_FLOAT, 0, v9 },
-{ "fcmpes",    CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055),        "7,e,f", F_FLOAT, 0, v9 },
-{ "fcmpes",    CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),        "8,e,f", F_FLOAT, 0, v9 },
-{ "fcmpes",    CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),        "9,e,f", F_FLOAT, 0, v9 },
+{ "fcmpd",               F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   F_FLOAT, 0, 0, v6 },
+{ "fcmpd",     CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052),        "6,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmpd",     CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052),        "7,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmpd",     CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052),        "8,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmpd",     CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052),        "9,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmped",              F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   F_FLOAT, 0, 0, v6 },
+{ "fcmped",    CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056),        "6,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmped",    CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056),        "7,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmped",    CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056),        "8,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmped",    CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056),        "9,v,B", F_FLOAT, 0, 0, v9 },
+{ "fcmpq",               F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT, 0, 0, v8 },
+{ "fcmpq",     CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),        "6,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpq",     CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpq",     CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpq",     CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpeq",              F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT, 0, 0, v8 },
+{ "fcmpeq",    CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),        "6,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpeq",    CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpeq",    CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpeq",    CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT, 0, 0, v9 },
+{ "fcmpx",               F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fcmpx",     CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),        "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpx",     CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpx",     CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpx",     CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpex",              F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 },
+{ "fcmpex",    CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),        "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpex",    CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpex",    CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmpex",    CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 },
+{ "fcmps",               F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   F_FLOAT, 0, 0, v6 },
+{ "fcmps",     CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051),        "6,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmps",     CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051),        "7,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmps",     CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051),        "8,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmps",     CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051),        "9,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmpes",              F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   F_FLOAT, 0, 0, v6 },
+{ "fcmpes",    CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055),        "6,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmpes",    CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055),        "7,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmpes",    CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),        "8,e,f", F_FLOAT, 0, 0, v9 },
+{ "fcmpes",    CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),        "9,e,f", F_FLOAT, 0, 0, v9 },
 
 /* These Extended FPop (FIFO) instructions are new in the Fujitsu
    MB86934, replacing the CPop instructions from v6 and later
    processors.  */
 
-#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, sparclite }
-#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op),        args, 0, 0, sparclite }
-#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0,  args, 0, 0, sparclite }
+#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, 0, sparclite }
+#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op),        args, 0, 0, 0, sparclite }
+#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0,  args, 0, 0, 0, sparclite }
 
 EFPOP1_2 ("efitod",    0x0c8, "f,H"),
 EFPOP1_2 ("efitos",    0x0c4, "f,g"),
@@ -1728,8 +1730,8 @@ EFPOP2_2 ("efcmpes",      0x055, "e,f"),
 
 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
    present.  Otherwise, the F_ALIAS flag is ignored.  */
-{ "cpop1",     F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 },
-{ "cpop2",     F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 },
+{ "cpop1",     F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 },
+{ "cpop2",     F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 },
 
 /* sparclet specific insns */
 
@@ -1741,26 +1743,26 @@ COMMUTEOP ("smacd", 0x2f, sparclet),
 COMMUTEOP ("umuld", 0x09, sparclet),
 COMMUTEOP ("smuld", 0x0d, sparclet),
 
-{ "shuffle",   F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),      "1,2,d", 0, 0, sparclet },
-{ "shuffle",   F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, 0, sparclet },
+{ "shuffle",   F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, sparclet },
+{ "shuffle",   F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, 0, 0, sparclet },
 
 /* The manual isn't completely accurate on these insns.  The `rs2' field is
    treated as being 6 bits to account for 6 bit immediates to cpush.  It is
    assumed that it is intended that bit 5 is 0 when rs2 contains a reg.  */
 #define BIT5 (1<<5)
-{ "crdcxt",    F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0),    "U,d", 0, 0, sparclet },
-{ "cwrcxt",    F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0),    "1,u", 0, 0, sparclet },
-{ "cpush",     F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0),     "1,2", 0, 0, sparclet },
-{ "cpush",     F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0),          "1,Y", 0, 0, sparclet },
-{ "cpusha",    F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0),     "1,2", 0, 0, sparclet },
-{ "cpusha",    F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0),          "1,Y", 0, 0, sparclet },
-{ "cpull",     F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, sparclet },
+{ "crdcxt",    F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0),    "U,d", 0, 0, 0, sparclet },
+{ "cwrcxt",    F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0),    "1,u", 0, 0, 0, sparclet },
+{ "cpush",     F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0),     "1,2", 0, 0, 0, sparclet },
+{ "cpush",     F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0),          "1,Y", 0, 0, 0, sparclet },
+{ "cpusha",    F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0),     "1,2", 0, 0, 0, sparclet },
+{ "cpusha",    F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0),          "1,Y", 0, 0, 0, sparclet },
+{ "cpull",     F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet },
 #undef BIT5
 
 /* sparclet coprocessor branch insns */
 #define SLCBCC2(opcode, mask, lose) \
- { opcode, (mask), ANNUL|(lose), "l",    F_DELAYED|F_CONDBR, 0, sparclet }, \
- { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, sparclet }
+ { opcode, (mask), ANNUL|(lose), "l",    F_DELAYED|F_CONDBR, 0, 0, sparclet }, \
+ { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, 0, sparclet }
 #define SLCBCC(opcode, mask) \
   SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
 
@@ -1786,280 +1788,318 @@ SLCBCC("cbnefr", 15),
 #undef SLCBCC2
 #undef SLCBCC
 
-{ "casa",      F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, v9andleon },
-{ "casa",      F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, v9andleon },
-{ "casxa",     F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, v9 },
-{ "casxa",     F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, v9 },
+{ "casa",      F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, 0, v9andleon },
+{ "casa",      F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, 0, v9andleon },
+{ "casxa",     F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, 0, v9 },
+{ "casxa",     F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, 0, v9 },
 
 /* v9 synthetic insns */
-{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, v9 }, /* bn,a,pt %xcc,label */
-{ "signx",     F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* sra rs1,%g0,rd */
-{ "signx",     F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* sra rd,%g0,rd */
-{ "clruw",     F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* srl rs1,%g0,rd */
-{ "clruw",     F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* srl rd,%g0,rd */
-{ "cas",       F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */
-{ "casl",      F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
-{ "casx",      F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
-{ "casxl",     F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
+{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, 0, v9 }, /* bn,a,pt %xcc,label */
+{ "signx",     F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* sra rs1,%g0,rd */
+{ "signx",     F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* sra rd,%g0,rd */
+{ "clruw",     F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* srl rs1,%g0,rd */
+{ "clruw",     F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* srl rd,%g0,rd */
+{ "cas",       F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */
+{ "casl",      F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
+{ "casx",      F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
+{ "casxl",     F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
 
 /* Ultrasparc extensions */
-{ "shutdown",  F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, v9a },
+{ "shutdown",  F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, 0, v9a },
 
 /* FIXME: Do we want to mark these as F_FLOAT, or something similar?  */
-{ "fpadd16",   F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fpadd16s",  F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fpadd32",   F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fpadd32s",  F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fpsub16",   F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fpsub16s",  F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fpsub32",   F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fpsub32s",  F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, v9a },
-
-{ "fpack32",   F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fpack16",   F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a },
-{ "fpackfix",  F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a },
-{ "fexpand",   F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, v9a },
-{ "fpmerge",   F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, v9a },
+{ "fpadd16",   F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fpadd16s",  F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fpadd32",   F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fpadd32s",  F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fpsub16",   F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fpsub16s",  F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fpsub32",   F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fpsub32s",  F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+
+{ "fpack32",   F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fpack16",   F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a },
+{ "fpackfix",  F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a },
+{ "fexpand",   F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, 0, v9a },
+{ "fpmerge",   F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, 0, v9a },
 
 /* Note that the mixing of 32/64 bit regs is intentional.  */
-{ "fmul8x16",          F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, v9a },
-{ "fmul8x16au",                F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, v9a },
-{ "fmul8x16al",                F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, v9a },
-{ "fmul8sux16",                F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fmul8ulx16",                F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fmuld8sux16",       F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, v9a },
-{ "fmuld8ulx16",       F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, v9a },
-
-{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "alignaddrl",        F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "faligndata",        F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, v9a },
-
-{ "fzerod",    F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, v9a },
-{ "fzero",     F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fzeros",    F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, v9a },
-{ "foned",     F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, v9a },
-{ "fone",      F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fones",     F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, v9a },
-{ "fsrc1d",    F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, v9a },
-{ "fsrc1",     F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fsrc1s",    F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, v9a },
-{ "fsrc2d",    F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, v9a },
-{ "fsrc2",     F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fsrc2s",    F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, v9a },
-{ "fnot1d",    F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, v9a },
-{ "fnot1",     F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fnot1s",    F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, v9a },
-{ "fnot2d",    F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, v9a },
-{ "fnot2",     F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fnot2s",    F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, v9a },
-{ "ford",      F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "for",       F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fors",      F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fnord",     F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fnor",      F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fnors",     F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fandd",     F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fand",      F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fands",     F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fnandd",    F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fnand",     F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fnands",    F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fxord",     F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fxor",      F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fxors",     F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fxnord",    F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fxnor",     F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fxnors",    F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fornot1d",  F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fornot1",   F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fornot1s",  F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fornot2d",  F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fornot2",   F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fornot2s",  F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fandnot1",  F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, v9a },
-{ "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, v9a },
-{ "fandnot2",  F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
-{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, v9a },
-
-{ "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpgt16",  F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmpgt32",  F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmple16",  F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fcmple32",  F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fpcmpune16",        F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fcmpne16",  F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fpcmpune32",        F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fcmpne32",  F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fpcmpueq16",        F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fcmpeq16",  F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, v9a },
-{ "fpcmpueq32",        F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "fcmpeq32",  F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
-
-{ "edge8cc",   F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge8lcc",  F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge16cc",  F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge32cc",  F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, v9a },
-
-{ "edge8",     F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "edge8l",    F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "edge16",    F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "edge16l",   F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "edge32",    F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
-{ "edge32l",   F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
-
-{ "pdist",     F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, v9a },
-
-{ "array8",    F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "array16",   F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, v9a },
-{ "array32",   F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, v9a },
+{ "fmul8x16",          F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fmul8x16au",                F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, 0, v9a },
+{ "fmul8x16al",                F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, 0, v9a },
+{ "fmul8sux16",                F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fmul8ulx16",                F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fmuld8sux16",       F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, 0, v9a },
+{ "fmuld8ulx16",       F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, 0, v9a },
+
+{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "alignaddrl",        F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "faligndata",        F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+
+{ "fzerod",    F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a },
+{ "fzero",     F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fzeros",    F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, 0, v9a },
+{ "foned",     F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, 0, v9a },
+{ "fone",      F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fones",     F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, 0, v9a },
+{ "fsrc1d",    F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, 0, v9a },
+{ "fsrc1",     F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fsrc1s",    F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, 0, v9a },
+{ "fsrc2d",    F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fsrc2",     F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fsrc2s",    F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fnot1d",    F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, 0, v9a },
+{ "fnot1",     F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fnot1s",    F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, 0, v9a },
+{ "fnot2d",    F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fnot2",     F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fnot2s",    F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, 0, v9a },
+{ "ford",      F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "for",       F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fors",      F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fnord",     F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fnor",      F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fnors",     F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fandd",     F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fand",      F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fands",     F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fnandd",    F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fnand",     F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fnands",    F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fxord",     F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fxor",      F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fxors",     F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fxnord",    F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fxnor",     F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fxnors",    F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fornot1d",  F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fornot1",   F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fornot1s",  F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fornot2d",  F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fornot2",   F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fornot2s",  F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fandnot1",  F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+{ "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "fandnot2",  F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, 0, v9a },
+
+{ "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fcmpgt16",  F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fcmpgt32",  F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fcmple16",  F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fcmple32",  F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fpcmpune16",        F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fcmpne16",  F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fpcmpune32",        F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fcmpne32",  F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fpcmpueq16",        F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fcmpeq16",  F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, 0, v9a },
+{ "fpcmpueq32",        F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "fcmpeq32",  F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+
+{ "edge8cc",   F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "edge8lcc",  F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "edge16cc",  F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "edge32cc",  F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+
+{ "edge8",     F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "edge8l",    F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "edge16",    F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "edge16l",   F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "edge32",    F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+{ "edge32l",   F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a },
+
+{ "pdist",     F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+
+{ "array8",    F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "array16",   F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, 0, v9a },
+{ "array32",   F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, 0, v9a },
 
 /* Cheetah instructions */
-{ "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", HWCAP_VIS2, 0, v9b },
-{ "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", HWCAP_VIS2, 0, v9b },
-{ "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", HWCAP_VIS2, 0, v9b },
-{ "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", HWCAP_VIS2, 0, v9b },
-{ "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", HWCAP_VIS2, 0, v9b },
-{ "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", HWCAP_VIS2, 0, v9b },
-
-{ "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", HWCAP_VIS2, 0, v9b },
-{ "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", HWCAP_VIS2, 0, v9b },
-
-{ "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", HWCAP_VIS2, 0, v9b },
-
-{ "commit",    F3(2, 0x3e, 0)|RD(30), F3(~2, ~0x3e, ~0)|RD(~30)|RS1_G0|SIMM13(~0), "", 0, HWCAP_TRANS, v9b },
-{ "fnadds",    F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
-{ "fnaddd",    F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
-{ "fnmuls",    F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
-{ "fnmuld",    F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
-{ "fhadds",    F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
-{ "fhaddd",    F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
-{ "fhsubs",    F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
-{ "fhsubd",    F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
-{ "fnhadds",   F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
-{ "fnhaddd",   F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
-{ "fnsmuld",   F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, v9b },
-{ "fpmaddx",   F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b },
-{ "fmadds",    F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fmaddd",    F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b },
-{ "fmsubs",    F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fmsubd",    F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fnmsubs",   F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fnmsubd",   F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fnmadds",   F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fnmaddd",   F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
-{ "fumadds",   F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fumaddd",   F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fumsubs",   F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fumsubd",   F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fnumsubs",  F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fnumsubd",  F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fnumadds",  F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "fnumaddd",  F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
-{ "addxc",     F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "addxccc",   F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "random",    F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT, HWCAP_RANDOM, v9b },
-{ "umulxhi",   F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "lzcnt",     F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b },
-{ "lzd",       F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, v9b },
-{ "cmask8",    F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, v9b },
-{ "cmask16",   F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, v9b },
-{ "cmask32",   F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, v9b },
-{ "fsll16",    F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fsrl16",    F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fsll32",    F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fsrl32",    F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fslas16",   F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fsra16",    F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fslas32",   F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fsra32",    F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "pdistn",    F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fmean16",   F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpadd64",   F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fchksm16",  F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpsub64",   F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpadds16",  F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, v9b },
-{ "fpadds32",  F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, v9b },
-{ "fpsubs16",  F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, v9b },
-{ "fpsubs32",  F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, v9b },
-{ "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, v9b },
-{ "movdtox",   F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, v9b },
-{ "movstouw",  F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, v9b },
-{ "movstosw",  F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, v9b },
-{ "movxtod",   F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, v9b },
-{ "movwtos",   F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, v9b },
-{ "xmulx",     F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "xmulxhi",   F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fucmple8",  F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
-{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fpcmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, v9b },
-{ "fucmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
-{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fucmpgt8",  F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
-{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
-{ "fpcmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, v9b },
-{ "fucmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
-{"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
-{ "des_ip",     F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b },
-{ "des_iip",    F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, v9b },
-{ "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, v9b },
-{"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, v9b },
-{ "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
-{"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
-{ "md5",        F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, v9b },
-{ "sha1",       F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, v9b },
-{ "sha256",     F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, v9b },
-{ "sha512",     F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, v9b },
-{ "crc32c",     F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, v9b },
-{ "mpmul",      F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
-{ "montmul",    F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
-{ "montsqr",    F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
-{"aes_eround01",  F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_eround23",  F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround01",  F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround23",  F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
-{"aes_kexpand1",  F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
-{"des_round",     F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
-{"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
-{"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
-{"camellia_f",    F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
-{ "flcmps",    CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmps",    CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmps",    CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmps",    CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmpd",    CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmpd",    CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmpd",    CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, v9b },
-{ "flcmpd",    CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, v9b },
+{ "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+{ "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+{ "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+{ "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+{ "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+{ "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+
+{ "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", HWCAP_VIS2, 0, 0, v9b },
+{ "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", HWCAP_VIS2, 0, 0, v9b },
+
+{ "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", HWCAP_VIS2, 0, 0, v9b },
+
+{ "fnadds",    F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fnaddd",    F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fnmuls",    F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fnmuld",    F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fhadds",    F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fhaddd",    F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fhsubs",    F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fhsubd",    F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fnhadds",   F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fnhaddd",   F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fnsmuld",   F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "fpmaddx",   F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9b },
+{ "fmadds",    F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fmaddd",    F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9b },
+{ "fmsubs",    F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fmsubd",    F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fnmsubs",   F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fnmsubd",   F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fnmadds",   F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fnmaddd",   F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9b },
+{ "fumadds",   F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fumaddd",   F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fumsubs",   F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fumsubd",   F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fnumsubs",  F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fnumsubd",  F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fnumadds",  F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "fnumaddd",  F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9b },
+{ "addxc",     F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, 0, v9b },
+{ "addxccc",   F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, 0, v9b },
+{ "umulxhi",   F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, 0, v9b },
+{ "lzcnt",     F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, 0, v9b },
+{ "lzd",       F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, 0, v9b },
+{ "cmask8",    F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, 0, v9b },
+{ "cmask16",   F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, 0, v9b },
+{ "cmask32",   F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, 0, v9b },
+{ "fsll16",    F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fsrl16",    F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fsll32",    F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fsrl32",    F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fslas16",   F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fsra16",    F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fslas32",   F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fsra32",    F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "pdistn",    F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, 0, v9b },
+{ "fmean16",   F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpadd64",   F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fchksm16",  F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpsub64",   F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpadds16",  F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, 0, v9b },
+{ "fpadds32",  F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, 0, v9b },
+{ "fpsubs16",  F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, 0, v9b },
+{ "fpsubs32",  F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, 0, v9b },
+{ "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, 0, v9b },
+{ "movdtox",   F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, 0, v9b },
+{ "movstouw",  F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9b },
+{ "movstosw",  F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9b },
+{ "movxtod",   F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, 0, v9b },
+{ "movwtos",   F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, 0, v9b },
+{ "xmulx",     F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9b },
+{ "xmulxhi",   F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, 0, v9b },
+{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, 0, v9b },
+{ "fucmple8",  F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b },
+{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, 0, v9b },
+{ "fpcmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9b },
+{ "fucmpne8",  F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b },
+{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, 0, v9b },
+{ "fucmpgt8",  F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b },
+{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, 0, v9b },
+{ "fpcmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9b },
+{ "fucmpeq8",  F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9b },
+{"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{ "des_ip",     F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, 0, v9b },
+{ "des_iip",    F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, 0, v9b },
+{ "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, 0, v9b },
+{"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, 0, v9b },
+{ "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9b },
+{"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9b },
+{ "md5",        F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, 0, v9b },
+{ "sha1",       F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9b },
+{ "sha256",     F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, 0, v9b },
+{ "sha512",     F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, 0, v9b },
+{ "crc32c",     F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, 0, v9b },
+{ "xmpmul",     F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMPMUL, v9b },
+{ "mpmul",      F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, 0, v9b },
+{ "xmontmul",   F3F(2, 0x36, 0x149)|RD(1), F3F(~2, ~0x36, ~0x149)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9b },
+{ "montmul",    F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, 0, v9b },
+{ "xmontsqr",   F3F(2, 0x36, 0x14a)|RD(1), F3F(~2, ~0x36, ~0x14a)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9b },
+{ "montsqr",    F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, 0, v9b },
+{"aes_eround01",  F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_eround23",  F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_dround01",  F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_dround23",  F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"aes_kexpand1",  F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, 0, v9b },
+{"des_round",     F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, 0, v9b },
+{"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9b },
+{"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9b },
+{"camellia_f",    F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9b },
+{ "flcmps",    CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmps",    CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmps",    CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmps",    CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmpd",    CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmpd",    CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmpd",    CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, 0, v9b },
+{ "flcmpd",    CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, 0, v9b },
+
+{ "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0),  "2", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait r */
+{ "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait imm */
+
+/* SPARC5 and VIS4.0 instructions.  */
+
+{ "subxc",      F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "subxccc",    F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
+
+{ "faligndatai", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9b },
+
+{ "fpadd8",     F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpadds8",    F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpaddus8",   F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpaddus16",  F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmple8",   F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpgt8",   F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmax8",     F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmax16",    F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmax32",    F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmaxu8",    F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmaxu16",   F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmaxu32",   F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmin8",     F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmin16",    F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmin32",    F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpminu8",    F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpminu16",   F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpminu32",   F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsub8",     F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsubs8",    F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsubus8",   F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsubus16",  F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
 
 /* More v9 specific insns, these need to come last so they do not clash
    with v9a instructions such as "edge8" which looks like impdep1. */
 
 #define IMPDEP(name, code) \
-{ name,        F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, v9notv9a }, \
-{ name,        F3(2, code, 1), F3(~2, ~code, ~1),         "1,i,d", 0, 0, v9notv9a }, \
-{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,1,2,d", 0, 0, v9notv9a }, \
-{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,e,f,g", 0, 0, v9notv9a }
+{ name,        F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9notv9a }, \
+{ name,        F3(2, code, 1), F3(~2, ~code, ~1),         "1,i,d", 0, 0, 0, v9notv9a }, \
+{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,1,2,d", 0, 0, 0, v9notv9a }, \
+{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,e,f,g", 0, 0, 0, v9notv9a }
 
 IMPDEP ("impdep1", 0x36),
 IMPDEP ("impdep2", 0x37),