clk:starfive: Add definition instead of numbers

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
index c39239b..54f9f17 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -16,25 +16,28 @@
 static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = {
        //source
        JH7110__DIV(JH7110_OSC_DIV4, "osc_div4", 4, JH7110_OSC),
-       JH7110__MUX(JH7110_AON_APB_FUNC, "aon_apb_func", 2,
+       JH7110__MUX(JH7110_AON_APB_FUNC, "aon_apb_func", PARENT_NUMS_2,
                        JH7110_OSC_DIV4,
                        JH7110_OSC),
        //gmac5
        JH7110_GATE(JH7110_U0_GMAC5_CLK_AHB, 
-                       "u0_dw_gmac5_axi64_clk_ahb", 0, JH7110_AON_AHB),
+                       "u0_dw_gmac5_axi64_clk_ahb",
+                       GATE_FLAG_NORMAL, JH7110_AON_AHB),
        JH7110_GATE(JH7110_U0_GMAC5_CLK_AXI,
-                       "u0_dw_gmac5_axi64_clk_axi", 0, JH7110_AON_AHB),
+                       "u0_dw_gmac5_axi64_clk_axi",
+                       GATE_FLAG_NORMAL, JH7110_AON_AHB),
        JH7110__DIV(JH7110_GMAC0_RMII_RTX,
                        "gmac0_rmii_rtx", 30, JH7110_GMAC0_RMII_REFIN),
        JH7110_GMUX(JH7110_U0_GMAC5_CLK_TX,
-                       "u0_dw_gmac5_axi64_clk_tx", 0, 2,
+                       "u0_dw_gmac5_axi64_clk_tx",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_GMAC0_GTXCLK,
                        JH7110_GMAC0_RMII_RTX),
        JH7110__INV(JH7110_U0_GMAC5_CLK_TX_INV,
                        "u0_dw_gmac5_axi64_clk_tx_inv",
                        JH7110_U0_GMAC5_CLK_TX),
        JH7110__MUX(JH7110_U0_GMAC5_CLK_RX,
-                       "u0_dw_gmac5_axi64_clk_rx", 2,
+                       "u0_dw_gmac5_axi64_clk_rx", PARENT_NUMS_2,
                        JH7110_GMAC0_RGMII_RXIN,
                        JH7110_GMAC0_RMII_RTX),
        JH7110__INV(JH7110_U0_GMAC5_CLK_RX_INV,
@@ -42,18 +45,21 @@ static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = {
                        JH7110_U0_GMAC5_CLK_RX),
        //otpc
        JH7110_GATE(JH7110_OTPC_CLK_APB,
-                       "u0_otpc_clk_apb", 0, JH7110_AON_APB),
+                       "u0_otpc_clk_apb",
+                       GATE_FLAG_NORMAL, JH7110_AON_APB),
        //rtc
        JH7110_GATE(JH7110_RTC_HMS_CLK_APB,
-                       "u0_rtc_hms_clk_apb", 0, JH7110_AON_APB),
+                       "u0_rtc_hms_clk_apb",
+                       GATE_FLAG_NORMAL, JH7110_AON_APB),
        JH7110__DIV(JH7110_RTC_INTERNAL,
                        "rtc_internal", 1022, JH7110_OSC),
        JH7110__MUX(JH7110_RTC_HMS_CLK_OSC32K,
-                       "u0_rtc_hms_clk_osc32k", 2,
+                       "u0_rtc_hms_clk_osc32k", PARENT_NUMS_2,
                        JH7110_CLK_RTC,
                        JH7110_RTC_INTERNAL),
        JH7110_GATE(JH7110_RTC_HMS_CLK_CAL,
-                       "u0_rtc_hms_clk_cal", 0, JH7110_OSC),
+                       "u0_rtc_hms_clk_cal",
+                       GATE_FLAG_NORMAL, JH7110_OSC),
 };
 
 int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev,

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
index a8b4b5e..09a8dc3 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
@@ -39,23 +39,26 @@ static const struct jh7110_clk_data jh7110_clk_isp_data[] __initconst = {
                        16, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
        JH7110__DIV(JH7110_U0_M31DPHY_TXCLKESC_LAN0, "u0_m31dphy_txclkesc_lan0",
                        60, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
-       JH7110_GATE(JH7110_U0_VIN_PCLK, "u0_vin_pclk", 0, JH7110_DOM4_APB),
+       JH7110_GATE(JH7110_U0_VIN_PCLK, "u0_vin_pclk",
+                       GATE_FLAG_NORMAL, JH7110_DOM4_APB),
        JH7110__DIV(JH7110_U0_VIN_SYS_CLK, "u0_vin_sys_clk",
                        8, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF0, "u0_vin_pixel_clk_if0",
-                       0, JH7110_MIPI_RX0_PXL),
+                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF1, "u0_vin_pixel_clk_if1",
-                       0, JH7110_MIPI_RX0_PXL),
+                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF2, "u0_vin_pixel_clk_if2",
-                       0, JH7110_MIPI_RX0_PXL),
+                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
        JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF3, "u0_vin_pixel_clk_if3",
-                       0, JH7110_MIPI_RX0_PXL),
-       JH7110__MUX(JH7110_U0_VIN_CLK_P_AXIWR, "u0_vin_clk_p_axiwr", 2,
+                       GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+       JH7110__MUX(JH7110_U0_VIN_CLK_P_AXIWR, "u0_vin_clk_p_axiwr",
+                       PARENT_NUMS_2,
                        JH7110_MIPI_RX0_PXL,
                        JH7110_DVP_INV),
        //ispv2_top_wrapper
        JH7110_GMUX(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C,
-                       "u0_ispv2_top_wrapper_clk_c", 0, 2,
+                       "u0_ispv2_top_wrapper_clk_c",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_MIPI_RX0_PXL,
                        JH7110_DVP_INV),
 };

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
index f9de3c1..3864b03 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -16,68 +16,68 @@
 static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
        //hifi4
        JH7110_GATE(JH7110_HIFI4_CLK_CORE, "u0_hifi4_clk_core",
-                       0, JH7110_HIFI4_CORE),
+                       GATE_FLAG_NORMAL, JH7110_HIFI4_CORE),
        //usb
        JH7110_GATE(JH7110_USB0_CLK_USB_APB, "u0_cdn_usb_clk_usb_apb",
-                       0, JH7110_STG_APB),
+                       GATE_FLAG_NORMAL, JH7110_STG_APB),
        JH7110_GATE(JH7110_USB0_CLK_UTMI_APB, "u0_cdn_usb_clk_utmi_apb",
-                       0, JH7110_STG_APB),
+                       GATE_FLAG_NORMAL, JH7110_STG_APB),
        JH7110_GATE(JH7110_USB0_CLK_AXI, "u0_cdn_usb_clk_axi",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GDIV(JH7110_USB0_CLK_LPM, "u0_cdn_usb_clk_lpm",
-                       0, 2, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 2, JH7110_OSC),
        JH7110_GDIV(JH7110_USB0_CLK_STB, "u0_cdn_usb_clk_stb",
-                       0, 4, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 4, JH7110_OSC),
        JH7110_GATE(JH7110_USB0_CLK_APP_125, "u0_cdn_usb_clk_app_125",
-                       0, JH7110_USB_125M),
+                       GATE_FLAG_NORMAL, JH7110_USB_125M),
        JH7110__DIV(JH7110_USB0_REFCLK, "u0_cdn_usb_refclk", 2, JH7110_OSC),
        //pci-e
        JH7110_GATE(JH7110_PCIE0_CLK_AXI_MST0, "u0_plda_pcie_clk_axi_mst0",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_PCIE0_CLK_APB, "u0_plda_pcie_clk_apb",
-                       0, JH7110_STG_APB),
+                       GATE_FLAG_NORMAL, JH7110_STG_APB),
        JH7110_GATE(JH7110_PCIE0_CLK_TL, "u0_plda_pcie_clk_tl",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_PCIE1_CLK_AXI_MST0, "u1_plda_pcie_clk_axi_mst0",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_PCIE1_CLK_APB, "u1_plda_pcie_clk_apb",
-                       0, JH7110_STG_APB),
+                       GATE_FLAG_NORMAL, JH7110_STG_APB),
        JH7110_GATE(JH7110_PCIE1_CLK_TL, "u1_plda_pcie_clk_tl",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_PCIE01_SLV_DEC_MAINCLK, "u0_pcie01_slv_dec_mainclk",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        //security
        JH7110_GATE(JH7110_SEC_HCLK, "u0_sec_top_hclk",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_SEC_MISCAHB_CLK, "u0_sec_top_miscahb_clk",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        //stg mtrx
        JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_MAIN, "u0_stg_mtrx_grp0_clk_main",
-                       0, JH7110_CPU_BUS),
+                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_BUS, "u0_stg_mtrx_grp0_clk_bus",
-                       0, JH7110_NOCSTG_BUS),
+                       GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_STG, "u0_stg_mtrx_grp0_clk_stg",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_MAIN, "u0_stg_mtrx_grp1_clk_main",
-                       0, JH7110_CPU_BUS),
+                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_BUS, "u0_stg_mtrx_grp1_clk_bus",
-                       0, JH7110_NOCSTG_BUS),
+                       GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_STG, "u0_stg_mtrx_grp1_clk_stg",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_HIFI, "u0_stg_mtrx_grp1_clk_hifi",
-                       0, JH7110_HIFI4_AXI),
+                       GATE_FLAG_NORMAL, JH7110_HIFI4_AXI),
        //e24_rvpi
        JH7110_GDIV(JH7110_E2_RTC_CLK, "u0_e2_sft7110_rtc_clk",
-                       0, 24, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 24, JH7110_OSC),
        JH7110_GATE(JH7110_E2_CLK_CORE, "u0_e2_sft7110_clk_core",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_E2_CLK_DBG, "u0_e2_sft7110_clk_dbg",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        //dw_sgdma1p
        JH7110_GATE(JH7110_DMA1P_CLK_AXI, "u0_dw_dma1p_8ch_56hs_clk_axi",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110_GATE(JH7110_DMA1P_CLK_AHB, "u0_dw_dma1p_8ch_56hs_clk_ahb",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
 };
 
 int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev,

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index c26d2ad..242f124 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -16,421 +16,438 @@
 
 static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
        /*root*/
-       JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", 2,
+       JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", PARENT_NUMS_2,
                        JH7110_OSC,
                        JH7110_PLL0_OUT),
        JH7110__DIV(JH7110_CPU_CORE, "cpu_core", 7, JH7110_CPU_ROOT),
        JH7110__DIV(JH7110_CPU_BUS, "cpu_bus", 2, JH7110_CPU_CORE),
-       JH7110__MUX(JH7110_GPU_ROOT, "gpu_root", 2,
+       JH7110__MUX(JH7110_GPU_ROOT, "gpu_root", PARENT_NUMS_2,
                        JH7110_PLL2_OUT,
                        JH7110_PLL1_OUT),
-       JH7110_MDIV(JH7110_PERH_ROOT, "perh_root", 2, 2,
+       JH7110_MDIV(JH7110_PERH_ROOT, "perh_root", 2, PARENT_NUMS_2,
                        JH7110_PLL0_OUT,
                        JH7110_PLL2_OUT),
-       JH7110__MUX(JH7110_BUS_ROOT, "bus_root", 2,
+       JH7110__MUX(JH7110_BUS_ROOT, "bus_root", PARENT_NUMS_2,
                        JH7110_OSC,
                        JH7110_PLL2_OUT),
        JH7110__DIV(JH7110_NOCSTG_BUS, "nocstg_bus", 3, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_AXI_CFG0, "axi_cfg0", 3, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_STG_AXIAHB, "stg_axiahb", 2, JH7110_AXI_CFG0),
-       JH7110_GATE(JH7110_AHB0, "ahb0", 0, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_AHB1, "ahb1", 0, JH7110_STG_AXIAHB),
+       JH7110_GATE(JH7110_AHB0, "ahb0", GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+       JH7110_GATE(JH7110_AHB1, "ahb1", GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
                        8, JH7110_STG_AXIAHB),
-       JH7110_GATE(JH7110_APB0, "apb0", 0, JH7110_APB_BUS),
+       JH7110_GATE(JH7110_APB0, "apb0", GATE_FLAG_NORMAL, JH7110_APB_BUS),
        JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
        JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),
        JH7110__DIV(JH7110_AUDIO_ROOT, "audio_root", 8, JH7110_PLL2_OUT),
        JH7110__DIV(JH7110_MCLK_INNER, "mclk_inner", 64, JH7110_AUDIO_ROOT),
-       JH7110__MUX(JH7110_MCLK, "mclk", 2,
+       JH7110__MUX(JH7110_MCLK, "mclk", PARENT_NUMS_2,
                        JH7110_MCLK_INNER,
                        JH7110_MCLK_EXT),
-       JH7110_GATE(JH7110_MCLK_OUT, "mclk_out", 0, JH7110_MCLK_INNER),
-       JH7110_MDIV(JH7110_ISP_2X, "isp_2x", 8, 2,
+       JH7110_GATE(JH7110_MCLK_OUT, "mclk_out", GATE_FLAG_NORMAL,
+                       JH7110_MCLK_INNER),
+       JH7110_MDIV(JH7110_ISP_2X, "isp_2x", 8, PARENT_NUMS_2,
                        JH7110_PLL2_OUT,
                        JH7110_PLL1_OUT),
        JH7110__DIV(JH7110_ISP_AXI, "isp_axi", 4, JH7110_ISP_2X),
-       JH7110_GDIV(JH7110_GCLK0, "gclk0", 0, 62, JH7110_PLL0_DIV2),
-       JH7110_GDIV(JH7110_GCLK1, "gclk1", 0, 62, JH7110_PLL1_DIV2),
-       JH7110_GDIV(JH7110_GCLK2, "gclk2", 0, 62, JH7110_PLL2_DIV2),
+       JH7110_GDIV(JH7110_GCLK0, "gclk0", GATE_FLAG_NORMAL,
+                       62, JH7110_PLL0_DIV2),
+       JH7110_GDIV(JH7110_GCLK1, "gclk1", GATE_FLAG_NORMAL,
+                       62, JH7110_PLL1_DIV2),
+       JH7110_GDIV(JH7110_GCLK2, "gclk2", GATE_FLAG_NORMAL,
+                       62, JH7110_PLL2_DIV2),
        /*u0_u7mc_sft7110*/
        JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
-                       0, JH7110_CPU_BUS),
+                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
        JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
                        6, JH7110_OSC),
        JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
-                       0, JH7110_CPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_CPU_CORE),
        JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
-                       0, JH7110_CPU_BUS),
+                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
        //NOC
        JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
                        "u0_sft7110_noc_bus_clk_cpu_axi",
-                       0, JH7110_CPU_BUS),
+                       GATE_FLAG_NORMAL, JH7110_CPU_BUS),
        JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI,
                        "u0_sft7110_noc_bus_clk_axicfg0_axi",
-                       0, JH7110_AXI_CFG0),
+                       GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
        //DDRC
        JH7110__DIV(JH7110_OSC_DIV2, "osc_div2", 2, JH7110_OSC),
        JH7110__DIV(JH7110_PLL1_DIV4, "pll1_div4", 2, JH7110_PLL1_DIV2),
        JH7110__DIV(JH7110_PLL1_DIV8, "pll1_div8", 2, JH7110_PLL1_DIV4),
-       JH7110__MUX(JH7110_DDR_BUS, "ddr_bus", 4,
+       JH7110__MUX(JH7110_DDR_BUS, "ddr_bus", PARENT_NUMS_4,
                        JH7110_OSC_DIV2,
                        JH7110_PLL1_DIV2,
                        JH7110_PLL1_DIV4,
                        JH7110_PLL1_DIV8),
        JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi",
-                       0, JH7110_DDR_BUS),
+                       GATE_FLAG_NORMAL, JH7110_DDR_BUS),
        //GPU
        JH7110__DIV(JH7110_GPU_CORE, "gpu_core", 7, JH7110_GPU_ROOT),
        JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk",
-                       0, JH7110_GPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_GPU_CORE),
        JH7110_GATE(JH7110_GPU_SYS_CLK, "u0_img_gpu_sys_clk",
-                       0, JH7110_AXI_CFG1),
+                       GATE_FLAG_NORMAL, JH7110_AXI_CFG1),
        JH7110_GATE(JH7110_GPU_CLK_APB, "u0_img_gpu_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GDIV(JH7110_GPU_RTC_TOGGLE, "u0_img_gpu_rtc_toggle",
-                       0, 12, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 12, JH7110_OSC),
        JH7110_GATE(JH7110_NOC_BUS_CLK_GPU_AXI,
                        "u0_sft7110_noc_bus_clk_gpu_axi",
-                       0, JH7110_GPU_CORE),
+                       GATE_FLAG_NORMAL, JH7110_GPU_CORE),
        //ISP
        JH7110_GATE(JH7110_ISP_TOP_CLK_ISPCORE_2X,
                        "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
-                       0, JH7110_ISP_2X),
+                       GATE_FLAG_NORMAL, JH7110_ISP_2X),
        JH7110_GATE(JH7110_ISP_TOP_CLK_ISP_AXI,
                        "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
-                       0, JH7110_ISP_AXI),
+                       GATE_FLAG_NORMAL, JH7110_ISP_AXI),
        JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI,
                        "u0_sft7110_noc_bus_clk_isp_axi",
-                       0, JH7110_ISP_AXI),
+                       GATE_FLAG_NORMAL, JH7110_ISP_AXI),
        //HIFI4
        JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
        JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
        //AXICFG1_DEC
        JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
-                       0, JH7110_AXI_CFG1),
+                       GATE_FLAG_NORMAL, JH7110_AXI_CFG1),
        JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
-                       0, JH7110_AHB0),
+                       GATE_FLAG_NORMAL, JH7110_AHB0),
        //VOUT
        JH7110_GATE(JH7110_VOUT_SRC,
                        "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
-                       0, JH7110_VOUT_ROOT),
+                       GATE_FLAG_NORMAL, JH7110_VOUT_ROOT),
        JH7110__DIV(JH7110_VOUT_AXI, "vout_axi", 7, JH7110_VOUT_ROOT),
        JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI,
                        "u0_sft7110_noc_bus_clk_disp_axi",
-                       0, JH7110_VOUT_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
        JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB,
                        "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
-                       0, JH7110_AHB1),
+                       GATE_FLAG_NORMAL, JH7110_AHB1),
        JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI,
                        "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
-                       0, JH7110_VOUT_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
        JH7110_GATE(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
                        "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk",
-                       0, JH7110_MCLK),
+                       GATE_FLAG_NORMAL, JH7110_MCLK),
        JH7110__DIV(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
                        "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref",
                        2, JH7110_OSC),
        //JPEGC
        JH7110__DIV(JH7110_JPEGC_AXI, "jpegc_axi", 16, JH7110_VENC_ROOT),
        JH7110_GATE(JH7110_CODAJ12_CLK_AXI, "u0_CODAJ12_clk_axi",
-                       0, JH7110_JPEGC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_JPEGC_AXI),
        JH7110_GDIV(JH7110_CODAJ12_CLK_CORE, "u0_CODAJ12_clk_core",
-                       0, 16, JH7110_VENC_ROOT),
+                       GATE_FLAG_NORMAL, 16, JH7110_VENC_ROOT),
        JH7110_GATE(JH7110_CODAJ12_CLK_APB, "u0_CODAJ12_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        //VDEC
        JH7110__DIV(JH7110_VDEC_AXI, "vdec_axi", 7, JH7110_BUS_ROOT),
        JH7110_GATE(JH7110_WAVE511_CLK_AXI, "u0_WAVE511_clk_axi",
-                       0, JH7110_VDEC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
        JH7110_GDIV(JH7110_WAVE511_CLK_BPU, "u0_WAVE511_clk_bpu",
-                       0, 7, JH7110_BUS_ROOT),
+                       GATE_FLAG_NORMAL, 7, JH7110_BUS_ROOT),
        JH7110_GDIV(JH7110_WAVE511_CLK_VCE, "u0_WAVE511_clk_vce",
-                       0, 7, JH7110_VDEC_ROOT),
+                       GATE_FLAG_NORMAL, 7, JH7110_VDEC_ROOT),
        JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk",
-                       0, JH7110_JPEGC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_JPEGC_AXI),
        JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk",
-                       0, JH7110_VDEC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
        JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI,
                        "u0_sft7110_noc_bus_clk_vdec_axi",
-                       0, JH7110_VDEC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
        //VENC
        JH7110__DIV(JH7110_VENC_AXI, "venc_axi", 15, JH7110_VENC_ROOT),
        JH7110_GATE(JH7110_WAVE420L_CLK_AXI, "u0_wave420l_clk_axi",
-                       0, JH7110_VENC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VENC_AXI),
        JH7110_GDIV(JH7110_WAVE420L_CLK_BPU, "u0_wave420l_clk_bpu",
-                       0, 15, JH7110_VENC_ROOT),
+                       GATE_FLAG_NORMAL, 15, JH7110_VENC_ROOT),
        JH7110_GDIV(JH7110_WAVE420L_CLK_VCE, "u0_wave420l_clk_vce",
-                       0, 15, JH7110_VENC_ROOT),
+                       GATE_FLAG_NORMAL, 15, JH7110_VENC_ROOT),
        JH7110_GATE(JH7110_WAVE420L_CLK_APB, "u0_wave420l_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_NOC_BUS_CLK_VENC_AXI,
                        "u0_sft7110_noc_bus_clk_venc_axi",
-                       0, JH7110_VENC_AXI),
+                       GATE_FLAG_NORMAL, JH7110_VENC_AXI),
        //INTMEM
        JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV,
                        "u0_axi_cfg0_dec_clk_main_div",
-                       0, JH7110_AHB1),
+                       GATE_FLAG_NORMAL, JH7110_AHB1),
        JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main",
-                       0, JH7110_AXI_CFG0),
+                       GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
        JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4",
-                       0, JH7110_HIFI4_AXI),
+                       GATE_FLAG_NORMAL, JH7110_HIFI4_AXI),
        JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi",
-                       0, JH7110_AXI_CFG0),
+                       GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
        //QSPI
        JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb",
-                       0, JH7110_AHB1),
+                       GATE_FLAG_NORMAL, JH7110_AHB1),
        JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src",
                        16, JH7110_GMACUSB_ROOT),
-       JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref", 0, 2,
+       JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_OSC,
                        JH7110_QSPI_REF_SRC),
        //SDIO
        JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb",
-                       0, JH7110_AHB0),
+                       GATE_FLAG_NORMAL, JH7110_AHB0),
        JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb",
-                       0, JH7110_AHB0),
+                       GATE_FLAG_NORMAL, JH7110_AHB0),
        JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard",
-                       0, 15, JH7110_AXI_CFG0),
+                       GATE_FLAG_NORMAL, 15, JH7110_AXI_CFG0),
        JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard",
-                       0, 15, JH7110_AXI_CFG0),
+                       GATE_FLAG_NORMAL, 15, JH7110_AXI_CFG0),
        //STG
        JH7110__DIV(JH7110_USB_125M, "usb_125m", 15, JH7110_GMACUSB_ROOT),
        JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI,
                        "u0_sft7110_noc_bus_clk_stg_axi",
-                       0, JH7110_NOCSTG_BUS),
+                       GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
        //GMAC1
        JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb",
-                       0, JH7110_AHB0),
+                       GATE_FLAG_NORMAL, JH7110_AHB0),
        JH7110_GATE(JH7110_GMAC5_CLK_AXI, "u1_dw_gmac5_axi64_clk_axi",
-                       0, JH7110_STG_AXIAHB),
+                       GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
        JH7110__DIV(JH7110_GMAC_SRC, "gmac_src", 7, JH7110_GMACUSB_ROOT),
        JH7110__DIV(JH7110_GMAC1_GTXCLK, "gmac1_gtxclk",
                        15, JH7110_GMACUSB_ROOT),
        JH7110__DIV(JH7110_GMAC1_RMII_RTX, "gmac1_rmii_rtx",
                        30, JH7110_GMAC1_RMII_REFIN),
        JH7110_GDIV(JH7110_GMAC5_CLK_PTP, "u1_dw_gmac5_axi64_clk_ptp",
-                       0, 31, JH7110_GMAC_SRC),
-       JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx", 2,
+                       GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
+       JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx",
+                       PARENT_NUMS_2,
                        JH7110_GMAC1_RGMII_RXIN,
                        JH7110_GMAC1_RMII_RTX),
        JH7110__INV(JH7110_GMAC5_CLK_RX_INV, "u1_dw_gmac5_axi64_clk_rx_inv",
                        JH7110_GMAC5_CLK_RX),
-       JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx", 0, 2,
+       JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx",
+                       GATE_FLAG_NORMAL, PARENT_NUMS_2,
                        JH7110_GMAC1_GTXCLK,
                        JH7110_GMAC1_RMII_RTX),
        JH7110__INV(JH7110_GMAC5_CLK_TX_INV, "u1_dw_gmac5_axi64_clk_tx_inv",
                        JH7110_GMAC5_CLK_TX),
        JH7110_GATE(JH7110_GMAC1_GTXC, "gmac1_gtxc",
-                       0, JH7110_GMAC1_GTXCLK),
+                       GATE_FLAG_NORMAL, JH7110_GMAC1_GTXCLK),
        //GMAC0
        JH7110_GDIV(JH7110_GMAC0_GTXCLK, "gmac0_gtxclk",
-                       0, 15, JH7110_GMACUSB_ROOT),
+                       GATE_FLAG_NORMAL, 15, JH7110_GMACUSB_ROOT),
        JH7110_GDIV(JH7110_GMAC0_PTP, "gmac0_ptp",
-                       0, 31, JH7110_GMAC_SRC),
+                       GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
        JH7110_GDIV(JH7110_GMAC_PHY, "gmac_phy",
-                       0, 31, JH7110_GMAC_SRC),
+                       GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
        JH7110_GATE(JH7110_GMAC0_GTXC, "gmac0_gtxc",
-                       0, JH7110_GMAC0_GTXCLK),
+                       GATE_FLAG_NORMAL, JH7110_GMAC0_GTXCLK),
        //SYS MISC
        JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        //CAN
        JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GDIV(JH7110_CAN0_CTRL_CLK_TIMER, "u0_can_ctrl_clk_timer",
-                       0, 24, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 24, JH7110_OSC),
        JH7110_GDIV(JH7110_CAN0_CTRL_CLK_CAN, "u0_can_ctrl_clk_can",
-                       0, 63, JH7110_PERH_ROOT),
+                       GATE_FLAG_NORMAL, 63, JH7110_PERH_ROOT),
        JH7110_GATE(JH7110_CAN1_CTRL_CLK_APB, "u1_can_ctrl_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GDIV(JH7110_CAN1_CTRL_CLK_TIMER, "u1_can_ctrl_clk_timer",
-                       0, 24, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 24, JH7110_OSC),
        JH7110_GDIV(JH7110_CAN1_CTRL_CLK_CAN, "u1_can_ctrl_clk_can",
-                       0, 63, JH7110_PERH_ROOT),
+                       GATE_FLAG_NORMAL, 63, JH7110_PERH_ROOT),
        //PWM
        JH7110_GATE(JH7110_PWM_CLK_APB, "u0_pwm_8ch_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        //WDT
        JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt",
-                       0, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        //TIMER
        JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
-                       CLK_IGNORE_UNUSED, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
-                       CLK_IGNORE_UNUSED, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
-                       CLK_IGNORE_UNUSED, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
-                       CLK_IGNORE_UNUSED, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
-                       CLK_IGNORE_UNUSED, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        //TEMP SENSOR
        JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GDIV(JH7110_TEMP_SENSOR_CLK_TEMP, "u0_temp_sensor_clk_temp",
-                       0, 24, JH7110_OSC),
+                       GATE_FLAG_NORMAL, 24, JH7110_OSC),
        //SPI
        JH7110_GATE(JH7110_SPI0_CLK_APB, "u0_ssp_spi_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_SPI1_CLK_APB, "u1_ssp_spi_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_SPI2_CLK_APB, "u2_ssp_spi_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_SPI3_CLK_APB, "u3_ssp_spi_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_SPI4_CLK_APB, "u4_ssp_spi_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_SPI5_CLK_APB, "u5_ssp_spi_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_SPI6_CLK_APB, "u6_ssp_spi_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        //I2C
        JH7110_GATE(JH7110_I2C0_CLK_APB, "u0_dw_i2c_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_I2C1_CLK_APB, "u1_dw_i2c_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_I2C2_CLK_APB, "u2_dw_i2c_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_I2C3_CLK_APB, "u3_dw_i2c_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_I2C4_CLK_APB, "u4_dw_i2c_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_I2C5_CLK_APB, "u5_dw_i2c_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        JH7110_GATE(JH7110_I2C6_CLK_APB, "u6_dw_i2c_clk_apb",
-                       0, JH7110_APB12),
+                       GATE_FLAG_NORMAL, JH7110_APB12),
        //UART
        JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
-                       0, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",
-                       0, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core",
-                       0, JH7110_OSC),
+                       GATE_FLAG_NORMAL, JH7110_OSC),
        JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core",
-                       0, 131071, JH7110_PERH_ROOT),
+                       GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT),
        JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core",
-                       0, 131071, JH7110_PERH_ROOT),
+                       GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT),
        JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core",
-                       0, 131071, JH7110_PERH_ROOT),
+                       GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT),
        //PWMDAC
        JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_PWMDAC_CLK_CORE, "u0_pwmdac_clk_core",
-                       0, 256, JH7110_AUDIO_ROOT),
+                       GATE_FLAG_NORMAL, 256, JH7110_AUDIO_ROOT),
        //SPDIF
        JH7110_GATE(JH7110_SPDIF_CLK_APB, "u0_cdns_spdif_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GATE(JH7110_SPDIF_CLK_CORE, "u0_cdns_spdif_clk_core",
-                       0, JH7110_MCLK),
+                       GATE_FLAG_NORMAL, JH7110_MCLK),
        //I2STX0_4CH0
        JH7110_GATE(JH7110_I2STX0_4CHCLK_APB, "u0_i2stx_4ch_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_I2STX_4CH0_BCLK_MST, "i2stx_4ch0_bclk_mst",
-                       0, 32, JH7110_MCLK),
+                       GATE_FLAG_NORMAL, 32, JH7110_MCLK),
        JH7110__INV(JH7110_I2STX_4CH0_BCLK_MST_INV, "i2stx_4ch0_bclk_mst_inv",
                        JH7110_I2STX_4CH0_BCLK_MST),
-       JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst", 64, 2,
+       JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst",
+                       64, PARENT_NUMS_2,
                        JH7110_I2STX_4CH0_BCLK_MST_INV,
                        JH7110_I2STX_4CH0_BCLK_MST),
-       JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk", 2,
+       JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk",
+                       PARENT_NUMS_2,
                        JH7110_I2STX_4CH0_BCLK_MST,
                        JH7110_I2STX_BCLK_EXT),
        JH7110__INV(JH7110_I2STX0_4CHBCLK_N, "u0_i2stx_4ch_bclk_n",
                        JH7110_I2STX0_4CHBCLK),
-       JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck", 2,
+       JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck",
+                       PARENT_NUMS_2,
                        JH7110_I2STX_4CH0_LRCK_MST,
                        JH7110_I2STX_LRCK_EXT),
        //I2STX1_4CH0
        JH7110_GATE(JH7110_I2STX1_4CHCLK_APB, "u1_i2stx_4ch_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_I2STX_4CH1_BCLK_MST, "i2stx_4ch1_bclk_mst",
-                       0, 32, JH7110_MCLK),
+                       GATE_FLAG_NORMAL, 32, JH7110_MCLK),
        JH7110__INV(JH7110_I2STX_4CH1_BCLK_MST_INV, "i2stx_4ch1_bclk_mst_inv",
                        JH7110_I2STX_4CH1_BCLK_MST),
-       JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst", 64, 2,
+       JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst",
+                       64, PARENT_NUMS_2,
                        JH7110_I2STX_4CH1_BCLK_MST_INV,
                        JH7110_I2STX_4CH1_BCLK_MST),
-       JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk", 2,
+       JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk",
+                       PARENT_NUMS_2,
                        JH7110_I2STX_4CH1_BCLK_MST,
                        JH7110_I2STX_BCLK_EXT),
        JH7110__INV(JH7110_I2STX1_4CHBCLK_N, "u1_i2stx_4ch_bclk_n",
                        JH7110_I2STX1_4CHBCLK),
-       JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck", 2,
+       JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck",
+                       PARENT_NUMS_2,
                        JH7110_I2STX_4CH1_LRCK_MST,
                        JH7110_I2STX_LRCK_EXT),
        //I2SRX_3CH
        JH7110_GATE(JH7110_I2SRX0_3CH_CLK_APB, "u0_i2srx_3ch_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_I2SRX_3CH_BCLK_MST, "i2srx_3ch_bclk_mst",
-                       0, 32, JH7110_MCLK),
+                       GATE_FLAG_NORMAL, 32, JH7110_MCLK),
        JH7110__INV(JH7110_I2SRX_3CH_BCLK_MST_INV, "i2srx_3ch_bclk_mst_inv",
                        JH7110_I2SRX_3CH_BCLK_MST),
-       JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst", 64, 2,
+       JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst",
+                       64, PARENT_NUMS_2,
                        JH7110_I2SRX_3CH_BCLK_MST_INV,
                        JH7110_I2SRX_3CH_BCLK_MST),
-       JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk", 2,
+       JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk",
+                       PARENT_NUMS_2,
                        JH7110_I2SRX_3CH_BCLK_MST,
                        JH7110_I2SRX_BCLK_EXT),
        JH7110__INV(JH7110_I2SRX0_3CH_BCLK_N, "u0_i2srx_3ch_bclk_n",
                        JH7110_I2SRX0_3CH_BCLK),
-       JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck", 2,
+       JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck",
+                       PARENT_NUMS_2,
                        JH7110_I2SRX_3CH_LRCK_MST,
                        JH7110_I2SRX_LRCK_EXT),
        //PDM_4MIC
        JH7110_GDIV(JH7110_PDM_CLK_DMIC, "u0_pdm_4mic_clk_dmic",
-                       0, 64, JH7110_MCLK),
+                       GATE_FLAG_NORMAL, 64, JH7110_MCLK),
        JH7110_GATE(JH7110_PDM_CLK_APB, "u0_pdm_4mic_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        //TDM
        JH7110_GATE(JH7110_TDM_CLK_AHB, "u0_tdm16slot_clk_ahb",
-                       0, JH7110_AHB0),
+                       GATE_FLAG_NORMAL, JH7110_AHB0),
        JH7110_GATE(JH7110_TDM_CLK_APB, "u0_tdm16slot_clk_apb",
-                       0, JH7110_APB0),
+                       GATE_FLAG_NORMAL, JH7110_APB0),
        JH7110_GDIV(JH7110_TDM_INTERNAL, "tdm_internal",
-                       0, 64, JH7110_MCLK),
-       JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm", 2,
+                       GATE_FLAG_NORMAL, 64, JH7110_MCLK),
+       JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm",
+                       PARENT_NUMS_2,
                        JH7110_TDM_INTERNAL,
                        JH7110_TDM_EXT),
        JH7110__INV(JH7110_TDM_CLK_TDM_N, "u0_tdm16slot_clk_tdm_n",

diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index 41225a0..9d58cd9 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -36,6 +36,15 @@
 /* isp PLL CLOCK offset */
 #define PLL_OFI(x)     (x - JH7110_CLK_ISP_REG_END)
 
+#define GATE_FLAG_NORMAL  0
+
+enum {
+       PARENT_NUMS_1 = 1,
+       PARENT_NUMS_2,
+       PARENT_NUMS_3,
+       PARENT_NUMS_4,
+};
+
 /* clock data */
 struct jh7110_clk_data {
        const char *name;