s5pc110: universal: Fix OneNAND IPL boot (not yet finished)

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

diff --git a/board/samsung/universal/lowlevel_init.S b/board/samsung/universal/lowlevel_init.S
index e1d95bb..f9f408e 100644 (file)
--- a/board/samsung/universal/lowlevel_init.S
+++ b/board/samsung/universal/lowlevel_init.S
@@ -80,7 +80,8 @@ lowlevel_init:
        str     r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
 
        /* IO retension release */
-       ldr     r0, =S5P_OTHERS                         @0xE0108200
+       ldreq   r0, =S5PC100_OTHERS                     @0xE0108200
+       ldrne   r0, =S5PC110_OTHERS                     @0xE010E000
        ldr     r1, [r0]
        ldr     r2, =(1 << 31)                          @IO_RET_REL
        orr     r1, r1, r2
@@ -140,14 +141,22 @@ lowlevel_init:
 
        bl      mem_ctrl_asm_init
 
+       cmp     r7, r8
        /* Wakeup support. Don't know if it's going to be used, untested. */
-       ldr     r0, =S5P_RST_STAT
+       ldreq   r0, =S5PC100_RST_STAT
+       ldrne   r0, =S5PC110_RST_STAT
        ldr     r1, [r0]
+       bne     110f
        bic     r1, r1, #0xfffffff7
-       cmp     r1, #0x8
+       mov     r2, #(1 << 3)
+       b       200f
+110:
+       bic     r1, r1, #0xfffeffff
+       mov     r2, #(1 << 16)
+200:
+       cmp     r1, r2
        beq     wakeup_reset
 #endif
-
 1:
        mov     lr, r9
        mov     pc, lr
@@ -169,12 +178,14 @@ wakeup_reset:
        str     r1, [r0, #S5PC1XX_GPIO_DAT_OFFSET]
 
        /* Clear wakeup status register */
-       ldr     r0, =S5P_WAKEUP_STAT
+       ldreq   r0, =S5PC100_WAKEUP_STAT
+       ldrne   r0, =S5PC110_WAKEUP_STAT
        ldr     r1, [r0]
        str     r1, [r0]
 
        /* Load return address and jump to kernel */
-       ldr     r0, =S5P_INFORM0
+       ldreq   r0, =S5PC100_INFORM0
+       ldrne   r0, =S5PC110_INFORM0
 
        /* r1 = physical address of s5pc100_cpu_resume function */
        ldr     r1, [r0]
@@ -231,13 +242,43 @@ system_clock_init:
        /* S5P_HPLL_CON */
        ldr     r1, =0x80600603         @ SDIV 3, PDIV 6, MDIV 96
        str     r1, [r0, #0x10C]
+
+       ldr     r1, [r0, #0x300]
+       ldr     r2, =0x00003fff
+       bic     r1, r1, r2
+#ifdef CONFIG_CLK_800_166_66
+       ldr     r2, =0x00011401
+#elif defined(CONFIG_CLK_500_166_66)
+       ldr     r2, =0x00011201
+#elif defined(CONFIG_CLK_666_166_66)
+       ldr     r2, =0x00011300
+#else
+       ldr     r2, =0x00011301
+#endif
+       orr     r1, r1, r2
+       str     r1, [r0, #0x300]
+       ldr     r1, [r0, #0x304]
+       ldr     r2, =0x00011110
+       orr     r1, r1, r2
+       str     r1, [r0, #0x304]
+       ldr     r1, =0x00000001
+       str     r1, [r0, #0x308]
+
+       /* Set Source Clock */
+       ldr     r1, =0x00001111                 @ A, M, E, HPLL Muxing
+       str     r1, [r0, #0x200]                @ S5PC1XX_CLK_SRC0
+
        b       200f
 110:
+       /* Set Clock divider */
+       ldr     r1, =0x14131330         @ 1:1:4:4, 1:4:5
+       str     r1, [r0, #0x300]
+
        /* Set Lock Time */
        ldr     r1, =0xe10                      @ Locktime : 0xe10 = 3600
        str     r1, [r0, #0x000]                @ S5PC110_APLL_LOCK
-       str     r1, [r0, #0x008]                @ S5PC110_MPLL_LOCK
-       str     r1, [r0, #0x010]                @ S5PC110_EPLL_LOCK
+       str     r1, [r0, #0x010]                @ S5PC110_MPLL_LOCK
+       str     r1, [r0, #0x018]                @ S5PC110_EPLL_LOCK
        str     r1, [r0, #0x020]                @ S5PC110_VPLL_LOCK
 
        /* S5PC110_APLL_CON */
@@ -253,22 +294,20 @@ system_clock_init:
        ldr     r1, =0x806C0603         @  54MHz
        str     r1, [r0, #0x120]
 
-200:
-       /* Set Clock divider */
-       ldr     r2, =0x14131330         @ 1:1:4:4, 1:4:5
-       str     r1, [r0, #0x300]
-
        /* Set Source Clock */
        ldr     r1, =0x10001111                 @ A, M, E, VPLL Muxing
        str     r1, [r0, #0x200]                @ S5PC1XX_CLK_SRC0
 
        /* OneDRAM(DMC0) clock setting */
-       ldr     r2, =0x01000000
-       orr     r1, r1, r2
+       ldr     r1, =0x01000000
        str     r1, [r0, #0x218]
        ldr     r1, =0x30000000
        str     r1, [r0, #0x318]
 
+       ldr     r1, =0x00909000
+       str     r1, [r0, #0x500]
+
+200:
        /* wait at least 200us to stablize all clock */
        mov     r2, #0x10000
 1:     subs    r2, r2, #1

diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h
index f4df890..e829fae 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/cpu.h
+++ b/include/asm-arm/arch-s5pc1xx/cpu.h
@@ -30,7 +30,6 @@
 #define S5P_ADDR(x)            (S5PC1XX_ADDR_BASE + (x))
 
 #define S5PC1XX_CLOCK_BASE     0xE0100000
-#define S5P_PA_PWR             S5P_ADDR(0x00108000)    /* Power Base */
 #define S5P_PA_CLK_OTHERS      S5P_ADDR(0x00200000)    /* Clock Others Base */
 
 /* Note that write the macro by address order */

diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/include/asm-arm/arch-s5pc1xx/power.h
index 951fbc9..ecffe7f 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/power.h
+++ b/include/asm-arm/arch-s5pc1xx/power.h
@@ -1,7 +1,6 @@
 /*
- * (C) Copyright 2009
- * Samsung Electronics, <www.samsung.com/sec>
- * Heungjun Kim <riverful.kim@samsung.com>
+ * Copyright (c) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
  * Minkyu Kang <mk7.kang@samsung.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -27,59 +26,16 @@
 /*
  * Power control
  */
-#define S5P_PWRREG(x)                  (S5P_PA_PWR + (x))
+#define S5PC100_OTHERS                 0xE0108200
+#define S5PC100_RST_STAT               0xE0108300
+#define S5PC100_SLEEP_WAKEUP           (1 << 3)
+#define S5PC100_WAKEUP_STAT            0xE0108304
+#define S5PC100_INFORM0                        0xE0108400
 
-#define S5P_PWR_CFG                    S5P_PWRREG(0x0)
-#define S5P_EINT_WAKEUP_MASK           S5P_PWRREG(0x04)
-#define S5P_NORMAL_CFG                 S5P_PWRREG(0x10)
-#define S5P_STOP_CFG                   S5P_PWRREG(0x14)
-#define S5P_SLEEP_CFG                  S5P_PWRREG(0x18)
-#define S5P_STOP_MEM_CFG               S5P_PWRREG(0x1c)
-#define S5P_OSC_FREQ                   S5P_PWRREG(0x100)
-#define S5P_OSC_STABLE                 S5P_PWRREG(0x104)
-#define S5P_PWR_STABLE                 S5P_PWRREG(0x108)
-#define S5P_INTERNAL_PWR_STABLE                S5P_PWRREG(0x110)
-#define S5P_CLAMP_STABLE               S5P_PWRREG(0x114)
-#define S5P_OTHERS                     S5P_PWRREG(0x200)
-#define S5P_RST_STAT                   S5P_PWRREG(0x300)
-#define S5P_WAKEUP_STAT                        S5P_PWRREG(0x304)
-#define S5P_BLK_PWR_STAT               S5P_PWRREG(0x308)
-#define S5P_INFORM0                    S5P_PWRREG(0x400)
-#define S5P_INFORM1                    S5P_PWRREG(0x404)
-#define S5P_INFORM2                    S5P_PWRREG(0x408)
-#define S5P_INFORM3                    S5P_PWRREG(0x40c)
-#define S5P_INFORM4                    S5P_PWRREG(0x410)
-#define S5P_INFORM5                    S5P_PWRREG(0x414)
-#define S5P_INFORM6                    S5P_PWRREG(0x418)
-#define S5P_INFORM7                    S5P_PWRREG(0x41c)
-#define S5P_DCGIDX_MAP0                        S5P_PWRREG(0x500)
-#define S5P_DCGIDX_MAP1                        S5P_PWRREG(0x504)
-#define S5P_DCGIDX_MAP2                        S5P_PWRREG(0x508)
-#define S5P_DCGPERF_MAP0               S5P_PWRREG(0x50c)
-#define S5P_DCGPERF_MAP1               S5P_PWRREG(0x510)
-#define S5P_DVCIDX_MAP                 S5P_PWRREG(0x514)
-#define S5P_FREQ_CPU                   S5P_PWRREG(0x518)
-#define S5P_FREQ_DPM                   S5P_PWRREG(0x51c)
-#define S5P_DVSEMCLK_EN                        S5P_PWRREG(0x520)
-#define S5P_APLL_CON_L8                        S5P_PWRREG(0x600)
-#define S5P_APLL_CON_L7                        S5P_PWRREG(0x604)
-#define S5P_APLL_CON_L6                        S5P_PWRREG(0x608)
-#define S5P_APLL_CON_L5                        S5P_PWRREG(0x60c)
-#define S5P_APLL_CON_L4                        S5P_PWRREG(0x610)
-#define S5P_APLL_CON_L3                        S5P_PWRREG(0x614)
-#define S5P_APLL_CON_L2                        S5P_PWRREG(0x618)
-#define S5P_APLL_CON_L1                        S5P_PWRREG(0x61c)
-#define S5P_EM_CONTROL                 S5P_PWRREG(0x620)
-
-#define S5P_CLKDIV_IEM_L8              S5P_PWRREG(0x700)
-#define S5P_CLKDIV_IEM_L7              S5P_PWRREG(0x704)
-#define S5P_CLKDIV_IEM_L6              S5P_PWRREG(0x708)
-#define S5P_CLKDIV_IEM_L5              S5P_PWRREG(0x70c)
-#define S5P_CLKDIV_IEM_L4              S5P_PWRREG(0x710)
-#define S5P_CLKDIV_IEM_L3              S5P_PWRREG(0x714)
-#define S5P_CLKDIV_IEM_L2              S5P_PWRREG(0x718)
-#define S5P_CLKDIV_IEM_L1              S5P_PWRREG(0x71c)
-
-#define S5P_IEM_HPMCLK_DIV             S5P_PWRREG(0x724)
+#define S5PC110_RST_STAT               0xE010A000
+#define S5PC110_SLEEP_WAKEUP           (1 << 3)
+#define S5PC110_WAKEUP_STAT            0xE010C200
+#define S5PC110_OTHERS                 0xE010E000
+#define S5PC110_INFORM0                        0xE010F000
 
 #endif