clk:starfive:Change PLL0 rate to 1.5GHz

Change PLL0 rate to 1.5GHz and change cpu_core divider.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
old mode 100755 (executable)
new mode 100644 (file)
index 42e6176..877bf04
--- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c
@@ -364,6 +364,41 @@ static int __init clk_starfive_jh7110_probe(struct platform_device *pdev)
        if (ret)
                return ret;
 
+/* set PLL0 default rate */
+#ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
+       if (PLL0_DEFAULT_FREQ) {
+               struct clk *pll0_clk = priv->pll_priv[PLL0_INDEX].hw.clk;
+               struct clk *cpu_root = priv->reg[JH7110_CPU_ROOT].hw.clk;
+               struct clk *osc_clk = clk_get(&pdev->dev, "osc");
+
+               if (IS_ERR(osc_clk))
+                       dev_err(&pdev->dev, "get osc_clk failed\n");
+
+               if (PLL0_DEFAULT_FREQ >= PLL0_FREQ_1500_VALUE) {
+                       struct clk *cpu_core = priv->reg[JH7110_CPU_CORE].hw.clk;
+
+                       if (clk_set_rate(cpu_core, PLL0_FREQ_1500_VALUE / 2)) {
+                               dev_err(&pdev->dev, "set cpu_core rate failed\n");
+                               goto failed_set;
+                       }
+               }
+
+               if (clk_set_parent(cpu_root, osc_clk)) {
+                       dev_err(&pdev->dev, "set parent to osc_clk failed\n");
+                       goto failed_set;
+               }
+
+               if (clk_set_rate(pll0_clk, PLL0_DEFAULT_FREQ))
+                       dev_err(&pdev->dev, "set pll0 rate failed\n");
+
+               if (clk_set_parent(cpu_root, pll0_clk))
+                       dev_err(&pdev->dev, "set parent to pll0_clk failed\n");
+
+failed_set:
+               clk_put(osc_clk);
+       }
+#endif
+
        ret = clk_starfive_jh7110_stg_init(pdev, priv);
        if (ret)
                return ret;

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
old mode 100755 (executable)
new mode 100644 (file)
index eb2511c..1668c22
--- a/drivers/clk/starfive/clk-starfive-jh7110-pll.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
@@ -13,6 +13,7 @@
  * If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2
  * frequency will be set the new rate during clock tree registering.
  */
+#define PLL0_DEFAULT_FREQ      PLL0_FREQ_1500_VALUE
 #define PLL2_DEFAULT_FREQ      PLL2_FREQ_1188_VALUE
 
 #define PLL0_INDEX             0