/* pipeline is NULL for shader objects. */
static void
-lvp_shader_lower(struct lvp_device *pdevice, struct lvp_pipeline *pipeline, nir_shader *nir, struct lvp_shader *shader, struct lvp_pipeline_layout *layout)
+lvp_shader_lower(struct lvp_device *pdevice, struct lvp_pipeline *pipeline, nir_shader *nir, struct lvp_pipeline_layout *layout)
{
if (nir->info.stage != MESA_SHADER_TESS_CTRL)
NIR_PASS_V(nir, remove_barriers, nir->info.stage == MESA_SHADER_COMPUTE || nir->info.stage == MESA_SHADER_MESH || nir->info.stage == MESA_SHADER_TASK);
}
nir_assign_io_var_locations(nir, nir_var_shader_out, &nir->num_outputs,
nir->info.stage);
+}
+static void
+lvp_shader_init(struct lvp_shader *shader, nir_shader *nir)
+{
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
if (impl->ssa_alloc > 100) //skip for small shaders
shader->inlines.must_inline = lvp_find_inlinable_uniforms(shader, nir);
struct lvp_shader *shader = &pipeline->shaders[stage];
nir_shader *nir;
VkResult result = compile_spirv(pdevice, sinfo, &nir);
- if (result == VK_SUCCESS)
- lvp_shader_lower(pdevice, pipeline, nir, shader, pipeline->layout);
+ if (result == VK_SUCCESS) {
+ lvp_shader_lower(pdevice, pipeline, nir, pipeline->layout);
+ lvp_shader_init(shader, nir);
+ }
return result;
}
pCreateInfo->pPushConstantRanges,
};
shader->layout = lvp_pipeline_layout_create(device, &pci, pAllocator);
- lvp_shader_lower(device, NULL, nir, shader, shader->layout);
+
+ if (pCreateInfo->codeType == VK_SHADER_CODE_TYPE_SPIRV_EXT)
+ lvp_shader_lower(device, NULL, nir, shader->layout);
+
+ lvp_shader_init(shader, nir);
+
lvp_shader_xfb_init(shader);
if (stage == MESA_SHADER_TESS_EVAL) {
/* spec requires that all tess modes are set in both shaders */