drm/i915: Fix up whitespace in some display chicken registers

Fix a bunch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-2-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a89e7a1..f6ca0d8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1334,8 +1334,8 @@
 
 #define ILK_DISPLAY_CHICKEN1   _MMIO(0x42000)
 #define   ILK_FBCQ_DIS         (1 << 22)
-#define   ILK_PABSTRETCH_DIS   REG_BIT(21)
-#define   ILK_SABSTRETCH_DIS   REG_BIT(20)
+#define   ILK_PABSTRETCH_DIS           REG_BIT(21)
+#define   ILK_SABSTRETCH_DIS           REG_BIT(20)
 #define   IVB_PRI_STRETCH_MAX_MASK     REG_GENMASK(21, 20)
 #define   IVB_PRI_STRETCH_MAX_X8       REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
 #define   IVB_PRI_STRETCH_MAX_X4       REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
@@ -2649,7 +2649,7 @@
 #define   PIPE_MISC_YUV420_MODE_FULL_BLEND     REG_BIT(26) /* glk+ */
 #define   PIPE_MISC_HDR_MODE_PRECISION         REG_BIT(23) /* icl+ */
 #define   PIPE_MISC_OUTPUT_COLORSPACE_YUV      REG_BIT(11)
-#define   PIPE_MISC_PIXEL_ROUNDING_TRUNC               REG_BIT(8) /* tgl+ */
+#define   PIPE_MISC_PIXEL_ROUNDING_TRUNC       REG_BIT(8) /* tgl+ */
 /*
  * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
  * valid values of: 6, 8, 10 BPC.
@@ -4528,8 +4528,8 @@
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE                (1 << 2)
 
 #define CHICKEN_PAR1_1                 _MMIO(0x42080)
-#define  IGNORE_KVMR_PIPE_A            REG_BIT(23)
-#define  KBL_ARB_FILL_SPARE_22         REG_BIT(22)
+#define   IGNORE_KVMR_PIPE_A           REG_BIT(23)
+#define   KBL_ARB_FILL_SPARE_22                REG_BIT(22)
 #define  DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
 #define  SKL_DE_COMPRESSED_HASH_MODE   (1 << 15)
 #define  DPA_MASK_VBLANK_SRD           (1 << 15)
@@ -4541,9 +4541,9 @@
 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
 
 #define CHICKEN_MISC_2         _MMIO(0x42084)
-#define  CHICKEN_MISC_DISABLE_DPT      REG_BIT(30) /* adl,dg2 */
-#define  KBL_ARB_FILL_SPARE_14 REG_BIT(14)
-#define  KBL_ARB_FILL_SPARE_13 REG_BIT(13)
+#define   CHICKEN_MISC_DISABLE_DPT     REG_BIT(30) /* adl,dg2 */
+#define   KBL_ARB_FILL_SPARE_14                REG_BIT(14)
+#define   KBL_ARB_FILL_SPARE_13                REG_BIT(13)
 #define  GLK_CL2_PWR_DOWN      (1 << 12)
 #define  GLK_CL1_PWR_DOWN      (1 << 11)
 #define  GLK_CL0_PWR_DOWN      (1 << 10)
@@ -4555,24 +4555,24 @@
 
 #define _CHICKEN_PIPESL_1_A    0x420b0
 #define _CHICKEN_PIPESL_1_B    0x420b4
-#define  HSW_PRI_STRETCH_MAX_MASK      REG_GENMASK(28, 27)
-#define  HSW_PRI_STRETCH_MAX_X8                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
-#define  HSW_PRI_STRETCH_MAX_X4                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
-#define  HSW_PRI_STRETCH_MAX_X2                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
-#define  HSW_PRI_STRETCH_MAX_X1                REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
-#define  HSW_SPR_STRETCH_MAX_MASK      REG_GENMASK(26, 25)
-#define  HSW_SPR_STRETCH_MAX_X8                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
-#define  HSW_SPR_STRETCH_MAX_X4                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
-#define  HSW_SPR_STRETCH_MAX_X2                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
-#define  HSW_SPR_STRETCH_MAX_X1                REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
+#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define   HSW_PRI_STRETCH_MAX_MASK     REG_GENMASK(28, 27)
+#define   HSW_PRI_STRETCH_MAX_X8       REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define   HSW_PRI_STRETCH_MAX_X4       REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define   HSW_PRI_STRETCH_MAX_X2       REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define   HSW_PRI_STRETCH_MAX_X1       REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define   HSW_SPR_STRETCH_MAX_MASK     REG_GENMASK(26, 25)
+#define   HSW_SPR_STRETCH_MAX_X8       REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define   HSW_SPR_STRETCH_MAX_X4       REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define   HSW_SPR_STRETCH_MAX_X2       REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define   HSW_SPR_STRETCH_MAX_X1       REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
 #define  HSW_FBCQ_DIS                  (1 << 22)
 #define  BDW_DPRS_MASK_VBLANK_SRD      (1 << 0)
-#define  SKL_PLANE1_STRETCH_MAX_MASK   REG_GENMASK(1, 0)
-#define  SKL_PLANE1_STRETCH_MAX_X8     REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
-#define  SKL_PLANE1_STRETCH_MAX_X4     REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
-#define  SKL_PLANE1_STRETCH_MAX_X2     REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
-#define  SKL_PLANE1_STRETCH_MAX_X1     REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
-#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define   SKL_PLANE1_STRETCH_MAX_MASK  REG_GENMASK(1, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X8    REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X4    REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
+#define   SKL_PLANE1_STRETCH_MAX_X2    REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
+#define   SKL_PLANE1_STRETCH_MAX_X1    REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
 
 #define _CHICKEN_TRANS_A       0x420c0
 #define _CHICKEN_TRANS_B       0x420c4
@@ -4590,18 +4590,18 @@
 #define MTL_CHICKEN_TRANS(trans)       _MMIO_TRANS((trans), \
                                                    _MTL_CHICKEN_TRANS_A, \
                                                    _MTL_CHICKEN_TRANS_B)
-#define  PIPE_VBLANK_WITH_DELAY                REG_BIT(31) /* ADL/DG2 */
-#define  HSW_FRAME_START_DELAY_MASK    REG_GENMASK(28, 27)
-#define  HSW_FRAME_START_DELAY(x)      REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
-#define  VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
-#define  FECSTALL_DIS_DPTSTREAM_DPTTG  REG_BIT(23)
-#define  DDI_TRAINING_OVERRIDE_ENABLE  REG_BIT(19)
-#define  ADLP_1_BASED_X_GRANULARITY    REG_BIT(18)
-#define  DDI_TRAINING_OVERRIDE_VALUE   REG_BIT(18)
-#define  DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
-#define  DDIE_TRAINING_OVERRIDE_VALUE  REG_BIT(16) /* CHICKEN_TRANS_A only */
-#define  PSR2_ADD_VERTICAL_LINE_COUNT  REG_BIT(15)
-#define  PSR2_VSC_ENABLE_PROG_HEADER   REG_BIT(12)
+#define   PIPE_VBLANK_WITH_DELAY       REG_BIT(31) /* ADL/DG2 */
+#define   HSW_FRAME_START_DELAY_MASK   REG_GENMASK(28, 27)
+#define   HSW_FRAME_START_DELAY(x)     REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
+#define   VSC_DATA_SEL_SOFTWARE_CONTROL        REG_BIT(25) /* GLK */
+#define   FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
+#define   DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
+#define   ADLP_1_BASED_X_GRANULARITY   REG_BIT(18)
+#define   DDI_TRAINING_OVERRIDE_VALUE  REG_BIT(18)
+#define   DDIE_TRAINING_OVERRIDE_ENABLE        REG_BIT(17) /* CHICKEN_TRANS_A only */
+#define   DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
+#define   PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
+#define   PSR2_VSC_ENABLE_PROG_HEADER  REG_BIT(12)
 
 #define DISP_ARB_CTL   _MMIO(0x45000)
 #define  DISP_FBC_MEMORY_WAKE          (1 << 31)