Merge tag 'irqchip-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm...

Pull irqchip updates for 5.1 from Marc Zyngier:

 - irqsteer error handling fix
 - GICv3 range coalescing fix
 - stm32 coprocessor coexistence fixes
 - mbigen MSI teardown fix
 - non-DT secondary GIC infrastructure removed
 - various cleanups (brcmstb-l2, mmp)
 - new DT bindings (r8a774c0)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
index 8de96a4..f977ea7 100644 (file)
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
@@ -16,6 +16,7 @@ Required properties:
     - "renesas,irqc-r8a7793" (R-Car M2-N)
     - "renesas,irqc-r8a7794" (R-Car E2)
     - "renesas,intc-ex-r8a774a1" (RZ/G2M)
+    - "renesas,intc-ex-r8a774c0" (RZ/G2E)
     - "renesas,intc-ex-r8a7795" (R-Car H3)
     - "renesas,intc-ex-r8a7796" (R-Car M3-W)
     - "renesas,intc-ex-r8a77965" (R-Car M3-N)

diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 7d5a44a..f676592 100644 (file)
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -90,7 +90,7 @@ void __init cns3xxx_map_io(void)
 /* used by entry-macro.S */
 void __init cns3xxx_init_irq(void)
 {
-       gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
+       gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
                 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
 }
 

diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index 83364fe..5e4ca13 100644 (file)
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -275,14 +275,14 @@ out_free:
        return ret;
 }
 
-int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
+static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
        struct device_node *parent)
 {
        return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
 }
 IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
 
-int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
+static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
        struct device_node *parent)
 {
        return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 2dd1ff0..7577755 100644 (file)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1482,7 +1482,7 @@ static int lpi_range_cmp(void *priv, struct list_head *a, struct list_head *b)
        ra = container_of(a, struct lpi_range, entry);
        rb = container_of(b, struct lpi_range, entry);
 
-       return rb->base_id - ra->base_id;
+       return ra->base_id - rb->base_id;
 }
 
 static void merge_lpi_ranges(void)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index ba2a37a..fd3110c 100644 (file)
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1089,11 +1089,10 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
 #endif
 }
 
-static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
+static int gic_init_bases(struct gic_chip_data *gic,
                          struct fwnode_handle *handle)
 {
-       irq_hw_number_t hwirq_base;
-       int gic_irqs, irq_base, ret;
+       int gic_irqs, ret;
 
        if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
                /* Frankein-GIC without banked registers... */
@@ -1145,28 +1144,21 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
        } else {                /* Legacy support */
                /*
                 * For primary GICs, skip over SGIs.
-                * For secondary GICs, skip over PPIs, too.
+                * No secondary GIC support whatsoever.
                 */
-               if (gic == &gic_data[0] && (irq_start & 31) > 0) {
-                       hwirq_base = 16;
-                       if (irq_start != -1)
-                               irq_start = (irq_start & ~31) + 16;
-               } else {
-                       hwirq_base = 32;
-               }
+               int irq_base;
 
-               gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
+               gic_irqs -= 16; /* calculate # of irqs to allocate */
 
-               irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
+               irq_base = irq_alloc_descs(16, 16, gic_irqs,
                                           numa_node_id());
                if (irq_base < 0) {
-                       WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-                            irq_start);
-                       irq_base = irq_start;
+                       WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
+                       irq_base = 16;
                }
 
                gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
-                                       hwirq_base, &gic_irq_domain_ops, gic);
+                                                   16, &gic_irq_domain_ops, gic);
        }
 
        if (WARN_ON(!gic->domain)) {
@@ -1195,7 +1187,6 @@ error:
 }
 
 static int __init __gic_init_bases(struct gic_chip_data *gic,
-                                  int irq_start,
                                   struct fwnode_handle *handle)
 {
        char *name;
@@ -1231,32 +1222,28 @@ static int __init __gic_init_bases(struct gic_chip_data *gic,
                gic_init_chip(gic, NULL, name, false);
        }
 
-       ret = gic_init_bases(gic, irq_start, handle);
+       ret = gic_init_bases(gic, handle);
        if (ret)
                kfree(name);
 
        return ret;
 }
 
-void __init gic_init(unsigned int gic_nr, int irq_start,
-                    void __iomem *dist_base, void __iomem *cpu_base)
+void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
 {
        struct gic_chip_data *gic;
 
-       if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
-               return;
-
        /*
         * Non-DT/ACPI systems won't run a hypervisor, so let's not
         * bother with these...
         */
        static_branch_disable(&supports_deactivate_key);
 
-       gic = &gic_data[gic_nr];
+       gic = &gic_data[0];
        gic->raw_dist_base = dist_base;
        gic->raw_cpu_base = cpu_base;
 
-       __gic_init_bases(gic, irq_start, NULL);
+       __gic_init_bases(gic, NULL);
 }
 
 static void gic_teardown(struct gic_chip_data *gic)
@@ -1399,7 +1386,7 @@ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
        if (ret)
                return ret;
 
-       ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
+       ret = gic_init_bases(*gic, &dev->of_node->fwnode);
        if (ret) {
                gic_teardown(*gic);
                return ret;
@@ -1459,7 +1446,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
        if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
                static_branch_disable(&supports_deactivate_key);
 
-       ret = __gic_init_bases(gic, -1, &node->fwnode);
+       ret = __gic_init_bases(gic, &node->fwnode);
        if (ret) {
                gic_teardown(gic);
                return ret;
@@ -1650,7 +1637,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
                return -ENOMEM;
        }
 
-       ret = __gic_init_bases(gic, -1, domain_handle);
+       ret = __gic_init_bases(gic, domain_handle);
        if (ret) {
                pr_err("Failed to initialise GIC\n");
                irq_domain_free_fwnode(domain_handle);

diff --git a/drivers/irqchip/irq-imx-irqsteer.c b/drivers/irqchip/irq-imx-irqsteer.c
index d1098f4..88df3d0 100644 (file)
--- a/drivers/irqchip/irq-imx-irqsteer.c
+++ b/drivers/irqchip/irq-imx-irqsteer.c
@@ -169,8 +169,12 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
 
        raw_spin_lock_init(&data->lock);
 
-       of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
-       of_property_read_u32(np, "fsl,channel", &data->channel);
+       ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
+       if (ret)
+               return ret;
+       ret = of_property_read_u32(np, "fsl,channel", &data->channel);
+       if (ret)
+               return ret;
 
        /*
         * There is one output irq for each group of 64 inputs.

diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index 567b29c..98b6e1d 100644 (file)
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -161,6 +161,9 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
        void __iomem *base = d->chip_data;
        u32 val;
 
+       if (!msg->address_lo && !msg->address_hi)
+               return;
+ 
        base += get_mbigen_vec_reg(d->hwirq);
        val = readl_relaxed(base);
 

diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 3496b61..8eed478 100644 (file)
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -179,7 +179,7 @@ static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
        return 0;
 }
 
-const struct irq_domain_ops mmp_irq_domain_ops = {
+static const struct irq_domain_ops mmp_irq_domain_ops = {
        .map            = mmp_irq_domain_map,
        .xlate          = mmp_irq_domain_xlate,
 };

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index a93296b..7bd1d4c 100644 (file)
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -716,7 +716,6 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
        const struct stm32_exti_bank *stm32_bank;
        struct stm32_exti_chip_data *chip_data;
        void __iomem *base = h_data->base;
-       u32 irqs_mask;
 
        stm32_bank = h_data->drv_data->exti_banks[bank_idx];
        chip_data = &h_data->chips_data[bank_idx];
@@ -725,21 +724,12 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
 
        raw_spin_lock_init(&chip_data->rlock);
 
-       /* Determine number of irqs supported */
-       writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
-       irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
-
        /*
         * This IP has no reset, so after hot reboot we should
         * clear registers to avoid residue
         */
        writel_relaxed(0, base + stm32_bank->imr_ofst);
        writel_relaxed(0, base + stm32_bank->emr_ofst);
-       writel_relaxed(0, base + stm32_bank->rtsr_ofst);
-       writel_relaxed(0, base + stm32_bank->ftsr_ofst);
-       writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
-       if (stm32_bank->fpr_ofst != UNDEF_REG)
-               writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
 
        pr_info("%pOF: bank%d\n", h_data->node, bank_idx);
 

diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 6261790..0f049b3 100644 (file)
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -158,8 +158,7 @@ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
  * Legacy platforms not converted to DT yet must use this to init
  * their GIC
  */
-void gic_init(unsigned int nr, int start,
-             void __iomem *dist , void __iomem *cpu);
+void gic_init(void __iomem *dist , void __iomem *cpu);
 
 int gicv2m_init(struct fwnode_handle *parent_handle,
                struct irq_domain *parent);