RiOTboard and MarSBoard: add new boards support
authorEric Benard <eric@eukrea.com>
Fri, 4 Apr 2014 17:05:55 +0000 (19:05 +0200)
committerStefano Babic <sbabic@denx.de>
Tue, 15 Apr 2014 10:23:57 +0000 (12:23 +0200)
RiOTboard is produced by Embest/Element 14 and is based on i.MX6 Solo
The following features are tested :
- UART2 (console)
- eMMC
- SDCard
- uSDCard
- Ethernet
- USB Host (through 4 ports hub)
- HDMI output
- I2C 1/2/3
- LVDS TFT with LCD8000-97C from Embest/Element 14

Boot on eMMC and through USB loader are tested.

For more informations on this board : http://www.riotboard.org/

MarSBoard is produced by Embest/Element 14 and is based on i.MX6 Dual
The following features are tested :
- UART2 (console)
- eMMC
- uSDCard
- Ethernet
- USB Host (through 2 ports hub)
- HDMI output
- I2C 1/2
- SPI NOR Flash
- LVDS TFT with LCD8000-97C from Embest/Element 14

Boot on SPI NOR and through USB loader are tested.

For more informations on this board :
http://www.embest-tech.com/shop/star/marsboard.html

Both boards are supported by the same code base as they are based on a
common trunk of schematics.

Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Stefano Babic <sbabic@denx.de>
board/embest/mx6boards/Makefile [new file with mode: 0644]
board/embest/mx6boards/mx6boards.c [new file with mode: 0644]
boards.cfg
include/configs/embestmx6boards.h [new file with mode: 0644]

diff --git a/board/embest/mx6boards/Makefile b/board/embest/mx6boards/Makefile
new file mode 100644 (file)
index 0000000..467fb50
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := mx6boards.o
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
new file mode 100644 (file)
index 0000000..6d86961
--- /dev/null
@@ -0,0 +1,607 @@
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ *         Fabio Estevam <fabio.estevam@freescale.com>
+ *         Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * based on sabresd.c which is :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * and on hummingboard.c which is :
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |                \
+       PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |                  \
+       PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |             \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
+       PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+                     PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+static int board_type = -1;
+#define BOARD_IS_MARSBOARD     0
+#define BOARD_IS_RIOTBOARD     1
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+       return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+       MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+       imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+       MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       /* GPIO16 -> AR8035 25MHz */
+       MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+       MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+       MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+       MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+       MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+       /* AR8035 PHY Reset */
+       MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+       /* AR8035 PHY Interrupt */
+       MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+       imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+       /* Reset AR8035 PHY */
+       gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
+       mdelay(2);
+       gpio_set_value(IMX_GPIO_NR(3, 31), 1);
+}
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+       /* from linux/arch/arm/mach-imx/mach-imx6q.c :
+        * Ar803x phy SmartEEE feature cause link status generates glitch,
+        * which cause ethernet link down/up issue, so disable SmartEEE
+        */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       mx6_rgmii_rework(phydev);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+       MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+       MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+       MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+       MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
+       MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+       MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+       MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+       MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       /* eMMC RST */
+       MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC2_BASE_ADDR},
+       {USDHC3_BASE_ADDR},
+       {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               ret = !gpio_get_value(USDHC2_CD_GPIO);
+               break;
+       case USDHC3_BASE_ADDR:
+               if (board_type == BOARD_IS_RIOTBOARD)
+                       ret = !gpio_get_value(USDHC3_CD_GPIO);
+               else if (board_type == BOARD_IS_MARSBOARD)
+                       ret = 1; /* eMMC/uSDHC3 is always present */
+               break;
+       case USDHC4_BASE_ADDR:
+               ret = 1; /* eMMC/uSDHC4 is always present */
+               break;
+       }
+
+       return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       s32 status = 0;
+       int i;
+
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-boot device node)    (Physical Port)
+        * ** RiOTboard :
+        * mmc0                    SDCard slot (bottom)
+        * mmc1                    uSDCard slot (top)
+        * mmc2                    eMMC
+        * ** MarSBoard :
+        * mmc0                    uSDCard slot (bottom)
+        * mmc1                    eMMC
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_direction_input(USDHC2_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       usdhc_cfg[0].max_bus_width = 4;
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+                       if (board_type == BOARD_IS_RIOTBOARD) {
+                               imx_iomux_v3_setup_multiple_pads(
+                                       riotboard_usdhc3_pads,
+                                       ARRAY_SIZE(riotboard_usdhc3_pads));
+                               gpio_direction_input(USDHC3_CD_GPIO);
+                               gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
+                               udelay(250);
+                               gpio_set_value(IMX_GPIO_NR(7, 8), 1);
+                       }
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       usdhc_cfg[1].max_bus_width = 4;
+                       break;
+               case 2:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+                       usdhc_cfg[2].max_bus_width = 4;
+                       gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
+                       udelay(250);
+                       gpio_set_value(IMX_GPIO_NR(6, 8), 1);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                              "(%d) then supported by the board (%d)\n",
+                              i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+                       return status;
+               }
+
+               status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+       }
+
+       return status;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+       MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+struct i2c_pads_info i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gp = IMX_GPIO_NR(5, 27)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gp = IMX_GPIO_NR(5, 26)
+       }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gp = IMX_GPIO_NR(4, 12)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gp = IMX_GPIO_NR(4, 13)
+       }
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gp = IMX_GPIO_NR(1, 5)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
+                               | MUX_PAD_CTRL(I2C_PAD_CTRL),
+               .gp = IMX_GPIO_NR(1, 6)
+       }
+};
+
+iomux_v3_cfg_t const tft_pads_riot[] = {
+       /* LCD_PWR_EN */
+       MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* TOUCH_INT */
+       MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* LED_PWR_EN */
+       MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* BL LEVEL */
+       MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const tft_pads_mars[] = {
+       /* LCD_PWR_EN */
+       MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* TOUCH_INT */
+       MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* LED_PWR_EN */
+       MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* BL LEVEL (PWM4) */
+       MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+       struct iomuxc *iomux = (struct iomuxc *)
+                               IOMUXC_BASE_ADDR;
+       setbits_le32(&iomux->gpr[2],
+                    IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
+       /* set backlight level to ON */
+       if (board_type == BOARD_IS_RIOTBOARD)
+               gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
+       else if (board_type == BOARD_IS_MARSBOARD)
+               gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
+}
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       /* set backlight level to OFF */
+       if (board_type == BOARD_IS_RIOTBOARD)
+               gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+       else if (board_type == BOARD_IS_MARSBOARD)
+               gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+
+       clrbits_le32(&iomux->gpr[2],
+                    IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
+}
+
+static int detect_hdmi(struct display_info_t const *dev)
+{
+       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+       return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+       disable_lvds(dev);
+       imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+       return (0 == i2c_set_bus_num(dev->bus)) &&
+               (0 == i2c_probe(dev->addr));
+}
+
+struct display_info_t const displays[] = {{
+       .bus    = -1,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = detect_hdmi,
+       .enable = do_enable_hdmi,
+       .mode   = {
+               .name           = "HDMI",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 2,
+       .addr   = 0x1,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = detect_i2c,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "LCD8000-97C",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 100,
+               .right_margin   = 200,
+               .upper_margin   = 10,
+               .lower_margin   = 20,
+               .hsync_len      = 20,
+               .vsync_len      = 8,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       int reg;
+
+       enable_ipu_clock();
+       imx_setup_hdmi();
+
+       /* Turn on LDB0, IPU,IPU DI0 clocks */
+       setbits_le32(&mxc_ccm->CCGR3,
+                    MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+       /* set LDB0 clk select to 011/011 */
+       clrsetbits_le32(&mxc_ccm->cs2cdr,
+                       MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+                       (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+       setbits_le32(&mxc_ccm->cscmr2,
+                    MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+       setbits_le32(&mxc_ccm->chsccdr,
+                    (CHSCCDR_CLK_SEL_LDB_DI0
+                    << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+       reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+            | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+            | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+            | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+            | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+            | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+            | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+            | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+       writel(reg, &iomux->gpr[2]);
+
+       clrsetbits_le32(&iomux->gpr[3],
+                       IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+                       IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
+                       IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+                       << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+       return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       setup_iomux_enet();
+
+       return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+       u32 cputype = cpu_type(get_cpu_rev());
+
+       switch (cputype) {
+       case MXC_CPU_MX6SOLO:
+               board_type = BOARD_IS_RIOTBOARD;
+               break;
+       case MXC_CPU_MX6D:
+               board_type = BOARD_IS_MARSBOARD;
+               break;
+       }
+
+       setup_iomux_uart();
+
+       if (board_type == BOARD_IS_RIOTBOARD)
+               imx_iomux_v3_setup_multiple_pads(
+                       tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
+       else if (board_type == BOARD_IS_MARSBOARD)
+               imx_iomux_v3_setup_multiple_pads(
+                       tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
+#if defined(CONFIG_VIDEO_IPUV3)
+       /* power ON LCD */
+       gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
+       /* touch interrupt is an input */
+       gpio_direction_input(IMX_GPIO_NR(6, 14));
+       /* power ON backlight */
+       gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
+       /* set backlight level to off */
+       if (board_type == BOARD_IS_RIOTBOARD)
+               gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+       else if (board_type == BOARD_IS_MARSBOARD)
+               gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+       setup_display();
+#endif
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+       /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
+       setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+       /* i2c2 : HDMI EDID */
+       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+       /* i2c3 : LVDS, Expansion connector */
+       setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
+       return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode riotboard_boot_modes[] = {
+       {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+       {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+       {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+       {NULL,   0},
+};
+static const struct boot_mode marsboard_boot_modes[] = {
+       {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+       {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+       {NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+       if (board_type == BOARD_IS_RIOTBOARD)
+               add_board_boot_modes(riotboard_boot_modes);
+       else if (board_type == BOARD_IS_RIOTBOARD)
+               add_board_boot_modes(marsboard_boot_modes);
+#endif
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: ");
+       if (board_type == BOARD_IS_MARSBOARD)
+               puts("MarSBoard\n");
+       else if (board_type == BOARD_IS_RIOTBOARD)
+               puts("RIoTboard\n");
+       else
+               printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
+
+       return 0;
+}
index b4203f1..9a87aa7 100644 (file)
@@ -328,6 +328,8 @@ Active  arm         armv7          mx6         gateworks       gw_ventana
 Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanaq1g                         gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024                                                  Tim Harvey <tharvey@gateworks.com>
 Active  arm         armv7          mx6         gateworks       gw_ventana          gwventanaq1gspi                      gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH                                        Tim Harvey <tharvey@gateworks.com>
 Active  arm         armv7          mx6         solidrun        hummingboard        hummingboard_solo                    hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512                                                      Jon Nettleton <jon.nettleton@gmail.com>
+Active  arm         armv7          mx6         embest          mx6boards           riotboard                            embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC                              Eric Bénard <eric@eukrea.com>
+Active  arm         armv7          mx6         embest          mx6boards           marsboard                            embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH                          Eric Bénard <eric@eukrea.com>
 Active  arm         armv7          omap3       -               overo               omap3_overo                          -                                                                                                                                 Steve Sakoman <sakoman@gmail.com>
 Active  arm         armv7          omap3       -               pandora             omap3_pandora                        -                                                                                                                                 Grazvydas Ignotas <notasas@gmail.com>
 Active  arm         armv7          omap3       8dtech          eco5pk              eco5pk                               -                                                                                                                                 Raphael Assenat <raph@8d.com>
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
new file mode 100644 (file)
index 0000000..eb91c44
--- /dev/null
@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ *
+ * Configuration settings for the Embest RIoTboard
+ *
+ * based on mx6*sabre*.h which are :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __RIOTBOARD_CONFIG_H
+#define __RIOTBOARD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_MXC_UART_BASE           UART2_BASE
+#define CONFIG_CONSOLE_DEV             "ttymxc0"
+#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"
+
+#define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_MX6
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED           100000
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET       /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                   ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE            RGMII
+#define CONFIG_ETHPRIME                        "FEC"
+#define CONFIG_FEC_MXC_PHYADDR         4
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS          0
+#define CONFIG_SF_DEFAULT_CS           (0 | (IMX_GPIO_NR(2, 30) << 8))
+#define CONFIG_SF_DEFAULT_SPEED                20000000
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY               1
+
+#define CONFIG_LOADADDR                        0x12000000
+#define CONFIG_SYS_TEXT_BASE           0x17800000
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+#define EMMC_ENV \
+       "emmcdev=2\0" \
+       "update_emmc_firmware=" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+                       "if mmc dev ${emmcdev}; then "  \
+                               "setexpr fw_sz ${filesize} / 0x200; " \
+                               "setexpr fw_sz ${fw_sz} + 1; "  \
+                               "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+                       "fi; "  \
+               "fi\0"
+#else
+#define EMMC_ENV ""
+#endif
+
+#ifdef CONFIG_CMD_SF
+#define SF_ENV \
+       "update_spi_firmware=" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "if ${get_cmd} ${update_spi_firmware_filename}; then " \
+                       "if sf probe; then "    \
+                               "sf erase 0 0xc0000; " \
+                               "sf write ${loadaddr} 0x400 ${filesize}; " \
+                       "fi; "  \
+               "fi\0"
+#else
+#define SF_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "script=boot.scr\0" \
+       "image=zImage\0" \
+       "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+       "fdt_addr=0x18000000\0" \
+       "boot_fdt=try\0" \
+       "ip_dyn=yes\0" \
+       "console=" CONFIG_CONSOLE_DEV "\0" \
+       "fdt_high=0xffffffff\0"   \
+       "initrd_high=0xffffffff\0" \
+       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+       "mmcpart=1\0" \
+       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+       "update_sd_firmware=" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "if mmc dev ${mmcdev}; then "   \
+                       "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+                               "setexpr fw_sz ${filesize} / 0x200; " \
+                               "setexpr fw_sz ${fw_sz} + 1; "  \
+                               "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+                       "fi; "  \
+               "fi\0" \
+       EMMC_ENV          \
+       SF_ENV    \
+       "mmcargs=setenv bootargs console=${console},${baudrate} " \
+               "root=${mmcroot}\0" \
+       "loadbootscript=" \
+               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi;\0" \
+       "netargs=setenv bootargs console=${console},${baudrate} " \
+               "root=/dev/nfs " \
+               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+       "netboot=echo Booting from net ...; " \
+               "run netargs; " \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${image}; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+       "mmc dev ${mmcdev};" \
+       "if mmc rescan; then " \
+               "if run loadbootscript; then " \
+               "run bootscript; " \
+               "else " \
+                       "if run loadimage; then " \
+                               "run mmcboot; " \
+                       "else run netboot; " \
+                       "fi; " \
+               "fi; " \
+       "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* RiOTboard */
+#define CONFIG_DEFAULT_FDT_FILE        "imx6s-riotboard.dtb"
+#define CONFIG_SYS_FSL_USDHC_NUM       3
+#define CONFIG_SYS_MMC_ENV_DEV         2       /* SDHC4 */
+#define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+/* MarSBoard */
+#define CONFIG_DEFAULT_FDT_FILE        "imx6q-marsboard.dtb"
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+#define CONFIG_ENV_OFFSET              (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE           (8 * 1024)
+#define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#endif                         /* __RIOTBOARD_CONFIG_H */