* gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.

	(do_sha1h): New function.
	(do_sha1su1): Likewise.
	(do_sha256su0): Likewise.
	(insns): Add 2 operand SHA instructions.
	* gas/testsuite/gas/arm/armv8-a+crypto.s: Update testcase.
	* gas/testsuite/gas/arm/armv8-a+crypto.d: Likewise.
	* opcodes/arm-dis.c (neon_opcodes): Add 2 operand sha instructions.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9253833..2e8b2ac 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+       * config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
+       (do_sha1h): New function.
+       (do_sha1su1): Likewise.
+       (do_sha256su0): Likewise.
+       (insns): Add 2 operand SHA instructions.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
        * config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
        (do_crypto_3op_1): New function.
        (do_sha1c): Likewise.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b648bca..ad4018b 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12352,7 +12352,9 @@ struct neon_tab_entry
   X(vrintr,    0xeb60a40, 0x3ba0400, N_INV),           \
   X(vrinta,    0xeb80a40, 0x3ba0400, N_INV),           \
   X(aes,       0x3b00300, N_INV,     N_INV),           \
-  X(sha3op,    0x2000c00, N_INV,     N_INV)
+  X(sha3op,    0x2000c00, N_INV,     N_INV),           \
+  X(sha1h,     0x3b902c0, N_INV,     N_INV),           \
+  X(sha2op,     0x3ba0380, N_INV,     N_INV)
 
 enum neon_opc
 {
@@ -16280,6 +16282,24 @@ do_sha256su1 (void)
 {
   do_crypto_3op_1 (1, 2);
 }
+
+static void
+do_sha1h (void)
+{
+  do_crypto_2op_1 (N_32, -1);
+}
+
+static void
+do_sha1su1 (void)
+{
+  do_crypto_2op_1 (N_32, 0);
+}
+
+static void
+do_sha256su0 (void)
+{
+  do_crypto_2op_1 (N_32, 1);
+}
 \f
 /* Overall per-instruction processing. */
 
@@ -18524,6 +18544,9 @@ static const struct asm_opcode insns[] =
   nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
   nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
   nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
+  nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
+  nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
+  nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
 
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 06c8a8a..129e62f 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,10 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+       * gas/arm/armv8-a+crypto.s: Update testcase.
+       * gas/arm/armv8-a+crypto.d: Likewise.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
        * gas/arm/armv8-a+crypto.d: Update testcase.
        * gas/arm/armv8-a+crypto.s: Likewise.
 

diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
index f0ed1f4..d5b2b4b 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a+crypto.d
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -50,6 +50,18 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f32eec4e    sha256su1.32    q7, q7, q7
 0[0-9a-f]+ <[^>]+> f3600ce0    sha256su1.32    q8, q8, q8
 0[0-9a-f]+ <[^>]+> f36eecee    sha256su1.32    q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3b902c0    sha1h.32        q0, q0
+0[0-9a-f]+ <[^>]+> f3b9e2ce    sha1h.32        q7, q7
+0[0-9a-f]+ <[^>]+> f3f902e0    sha1h.32        q8, q8
+0[0-9a-f]+ <[^>]+> f3f9e2ee    sha1h.32        q15, q15
+0[0-9a-f]+ <[^>]+> f3ba0380    sha1su1.32      q0, q0
+0[0-9a-f]+ <[^>]+> f3bae38e    sha1su1.32      q7, q7
+0[0-9a-f]+ <[^>]+> f3fa03a0    sha1su1.32      q8, q8
+0[0-9a-f]+ <[^>]+> f3fae3ae    sha1su1.32      q15, q15
+0[0-9a-f]+ <[^>]+> f3ba03c0    sha256su0.32    q0, q0
+0[0-9a-f]+ <[^>]+> f3bae3ce    sha256su0.32    q7, q7
+0[0-9a-f]+ <[^>]+> f3fa03e0    sha256su0.32    q8, q8
+0[0-9a-f]+ <[^>]+> f3fae3ee    sha256su0.32    q15, q15
 0[0-9a-f]+ <[^>]+> efa0 0e00   vmull.p64       q0, d0, d0
 0[0-9a-f]+ <[^>]+> efef eeaf   vmull.p64       q15, d31, d31
 0[0-9a-f]+ <[^>]+> ffb0 0300   aese.8  q0, q0
@@ -96,3 +108,15 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> ff2e ec4e   sha256su1.32    q7, q7, q7
 0[0-9a-f]+ <[^>]+> ff60 0ce0   sha256su1.32    q8, q8, q8
 0[0-9a-f]+ <[^>]+> ff6e ecee   sha256su1.32    q15, q15, q15
+0[0-9a-f]+ <[^>]+> ffb9 02c0   sha1h.32        q0, q0
+0[0-9a-f]+ <[^>]+> ffb9 e2ce   sha1h.32        q7, q7
+0[0-9a-f]+ <[^>]+> fff9 02e0   sha1h.32        q8, q8
+0[0-9a-f]+ <[^>]+> fff9 e2ee   sha1h.32        q15, q15
+0[0-9a-f]+ <[^>]+> ffba 0380   sha1su1.32      q0, q0
+0[0-9a-f]+ <[^>]+> ffba e38e   sha1su1.32      q7, q7
+0[0-9a-f]+ <[^>]+> fffa 03a0   sha1su1.32      q8, q8
+0[0-9a-f]+ <[^>]+> fffa e3ae   sha1su1.32      q15, q15
+0[0-9a-f]+ <[^>]+> ffba 03c0   sha256su0.32    q0, q0
+0[0-9a-f]+ <[^>]+> ffba e3ce   sha256su0.32    q7, q7
+0[0-9a-f]+ <[^>]+> fffa 03e0   sha256su0.32    q8, q8
+0[0-9a-f]+ <[^>]+> fffa e3ee   sha256su0.32    q15, q15

diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
index f6aac5a..679f604 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a+crypto.s
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -49,7 +49,18 @@
        sha256su1.32    q7, q7, q7
        sha256su1.32    q8, q8, q8
        sha256su1.32    q15, q15, q15
-
+       sha1h.32        q0, q0
+       sha1h.32        q7, q7
+       sha1h.32        q8, q8
+       sha1h.32        q15, q15
+       sha1su1.32      q0, q0
+       sha1su1.32      q7, q7
+       sha1su1.32      q8, q8
+       sha1su1.32      q15, q15
+       sha256su0.32    q0, q0
+       sha256su0.32    q7, q7
+       sha256su0.32    q8, q8
+       sha256su0.32    q15, q15
 
        .thumb
        vmull.p64       q0, d0, d0
@@ -98,3 +109,15 @@
        sha256su1.32    q7, q7, q7
        sha256su1.32    q8, q8, q8
        sha256su1.32    q15, q15, q15
+       sha1h.32        q0, q0
+       sha1h.32        q7, q7
+       sha1h.32        q8, q8
+       sha1h.32        q15, q15
+       sha1su1.32      q0, q0
+       sha1su1.32      q7, q7
+       sha1su1.32      q8, q8
+       sha1su1.32      q15, q15
+       sha256su0.32    q0, q0
+       sha256su0.32    q7, q7
+       sha256su0.32    q8, q8
+       sha256su0.32    q15, q15

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 23d7975..f540080 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+       * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
        * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
 
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 97a96d1..8a7dc0f 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -590,6 +590,9 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
   {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
+  {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
+  {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
+  {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},