drm/amdkfd: Add PM4 target XCC

In a device that supports multiple XCCs, unlike AQL queues, the PM4 queue
will be only processed in one XCC in the partitioning. This patch
re-purposes the queue percentage variable in create queue and update
queue ioctl for the user space to specify the target XCC.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Tested-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index eb0b0b38f10eb0b1c925125b6bb31772b8e92fa9..45e8da125f70b9f318cb1d0b3209a895ebb7cae2 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -186,7 +186,12 @@ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
 static int set_queue_properties_from_user(struct queue_properties *q_properties,
                                struct kfd_ioctl_create_queue_args *args)
 {
-       if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
+       /*
+        * Repurpose queue percentage to accommodate new features:
+        * bit 0-7: queue percentage
+        * bit 8-15: pm4_target_xcc
+        */
+       if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
                pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
                return -EINVAL;
        }
@@ -236,7 +241,9 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,
 
        q_properties->is_interop = false;
        q_properties->is_gws = false;
-       q_properties->queue_percent = args->queue_percentage;
+       q_properties->queue_percent = args->queue_percentage & 0xFF;
+       /* bit 8-15 are repurposed to be PM4 target XCC */
+       q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
        q_properties->priority = args->queue_priority;
        q_properties->queue_address = args->ring_base_address;
        q_properties->queue_size = args->ring_size;
@@ -442,7 +449,12 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
        struct kfd_ioctl_update_queue_args *args = data;
        struct queue_properties properties;
 
-       if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
+       /*
+        * Repurpose queue percentage to accommodate new features:
+        * bit 0-7: queue percentage
+        * bit 8-15: pm4_target_xcc
+        */
+       if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
                pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
                return -EINVAL;
        }
@@ -466,7 +478,9 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
 
        properties.queue_address = args->ring_base_address;
        properties.queue_size = args->ring_size;
-       properties.queue_percent = args->queue_percentage;
+       properties.queue_percent = args->queue_percentage & 0xFF;
+       /* bit 8-15 are repurposed to be PM4 target XCC */
+       properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
        properties.priority = args->queue_priority;
 
        pr_debug("Updating queue id %d for pasid 0x%x\n",

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index c677322057dd91b2b9787983718875c4c27cf2cd..b46c984b3a1793fe2d10ffea51984e36ed821370 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -587,6 +587,7 @@ static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
                        /* PM4 Queue */
                        m->compute_current_logic_xcc_id = 0;
                        m->compute_tg_chunk_size = 0;
+                       m->pm4_target_xcc_in_xcp = q->pm4_target_xcc;
                }
 
                if (xcc == 0) {
@@ -627,6 +628,7 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
                        /* PM4 Queue */
                        m->compute_current_logic_xcc_id = 0;
                        m->compute_tg_chunk_size = 0;
+                       m->pm4_target_xcc_in_xcp = q->pm4_target_xcc;
                }
        }
 }

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 873b49238dc1573907d0224e3d6932ee54d459bb..1337fcdf8958a0ea35f6c0e317d519f729611f13 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -509,6 +509,7 @@ struct queue_properties {
        bool is_evicted;
        bool is_active;
        bool is_gws;
+       uint32_t pm4_target_xcc;
        /* Not relevant for user mode queues in cp scheduling */
        unsigned int vmid;
        /* Relevant only for sdma queues*/

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index b1fb017b2ef883fb02250a8b259801e41e7c115b..2b2ae0c9902bd45af8a674d48d9a250cafb5e7e9 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -477,6 +477,7 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm,
        pqn->q->properties.queue_size = p->queue_size;
        pqn->q->properties.queue_percent = p->queue_percent;
        pqn->q->properties.priority = p->priority;
+       pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc;
 
        retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
                                                        pqn->q, NULL);