[binutils][aarch64] New sve_size_bh iclass.

Add new iclass sve_size_bh to handle instructions that have two variants
encoded with the SVE_sz field.
This iclass behaves the same as the sve_size_sd iclass, but it has a
nicer name for those instructions that choose between variants using the
"B" and "H" size qualifiers.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_bh iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_bh iclass decode.

diff --git a/include/ChangeLog b/include/ChangeLog
index 3d17921..28e00bf 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
+       * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
        * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
 
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8749993..0df8bdd 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -594,6 +594,7 @@ enum aarch64_insn_class
   sve_size_hsd,
   sve_size_hsd2,
   sve_size_sd,
+  sve_size_bh,
   sve_size_sd2,
   testbranch,
   cryptosm3,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f139282..d0f28ce 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,13 @@
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+       sve_size_bh iclass encode.
+       * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+       sve_size_bh iclass decode.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
        sve_size_sd2 iclass encode.
        * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
        sve_size_sd2 iclass decode.

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 6627b54..674eba5 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1655,6 +1655,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
       insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
       break;
 
+    case sve_size_bh:
     case sve_size_sd:
       insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
       break;

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 35576b3..bfc47b4 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2806,6 +2806,7 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       variant = i - 1;
       break;
 
+    case sve_size_bh:
     case sve_size_sd:
       variant = extract_field (FLD_SVE_sz, inst->value, 0);
       break;