static DEFINE_SPINLOCK(irq_button_lock);
static DEFINE_SPINLOCK(irq_detect_lock);
+#ifdef CONFIG_SND_SOC_SPRD_USE_EAR_JACK_TYPE13
static DEFINE_SPINLOCK(irq_detect_mic_lock);
+#endif
static int detect_err_count = 0;
static int debug_level = 0;
#define SOC_REG(r) ((unsigned short)(r))
-static uint32_t s_ana_int_done=0;
uint32_t impd_adc_value = 0;
int impd_isr;
headset_reg_set_val(HEADMIC_DETECT_REG(ANA_PMU0), 0x0700, 0x0000, 0);
headset_reg_set_val(HEADMIC_DETECT_REG(ANA_CDC3), 0xC000, 0x0000, 0);
-
+ return 0;
}
uint32_t __sprd_codec_impd_mcu_test(void){
- int i;
int timewait=0;
uint32_t val;
- uint32_t test_cnt;
/*the register listed below need to be configured before the software reset of IMPD ADC.*/
/*for the asic standard values with reg 0x40038670 is 0x73C8 or 0x7380*/
PRINT_INFO("summer.wang impd_mcu step8 AUDIO_CTRL = 0x%08x\n",sci_adi_read(AUDIO_CTRL));
/*9.read adc :0x40038004*/
+ /*
// val = sci_adi_read(AUDIO_DATA);
// PRINT_INFO("summer.wang impd_mcu step9 adc_val = 0x%08x\n",val);
-/* test_cnt=0;
+ test_cnt=0;
while(test_cnt++<0x100){
val = sci_adi_read(AUDIO_DATA);
- /*for avoidig overflow*//*
+ // for avoidig overflow
if(val != 0x1fff)
PRINT_INFO("summer.wang impd_mcu step9 adc_val = 0x%08x\n",val);
}
-*/
+ */
+
/*10.CUR_EN = 0 */
headset_reg_clr_bit(HEADMIC_DETECT_REG(ANA_HDT2),AUD_IMPD_CUR_EN);
return;
}
+#ifdef CONFIG_SND_SOC_SPRD_USE_EAR_JACK_TYPE13
static void headset_irq_detect_mic_enable(int enable, unsigned int irq)
{
unsigned long spin_lock_flags;
spin_unlock_irqrestore(&irq_detect_mic_lock, spin_lock_flags);
return;
}
+#endif
static void headmic_sleep_disable(struct device *dev, int on)
{
SPRD_HEADSET_TYPE headset_type;
int plug_state_current = 0;
int gpio_detect_value_current = 0;
+ int readtimes=0;
+ uint32_t val_impd=0;
+ static int value_current=0;
down(&headset_sem);
ENTER;
if(0 == plug_state_last){
PRINT_INFO("summer wang headset_impd 01\n");
headset_impd_int();
- int i=0;
- int readtimes=0;
- uint32_t val_impd=0;
- static int value_current=0;
val_impd = __sprd_codec_impd_mcu_test();
value_current = gpio_get_value(pdata->gpio_detect);
return IRQ_HANDLED;
}
+#ifdef CONFIG_SND_SOC_SPRD_USE_EAR_JACK_TYPE13
static irqreturn_t headset_detect_mic_irq_handler(int irq, void *dev)
{
struct sprd_headset *ht = dev;
PRINT_INFO("headset_detect_mic_irq_handler out1 \n");
return IRQ_HANDLED;
}
+#endif
+
static ssize_t key_state_onoff_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
static int headset_detect_probe(struct platform_device *pdev)
{
- PRINT_INFO("summer.wang headset_detect_probe");
struct sprd_headset_platform_data *pdata = pdev->dev.platform_data;
struct sprd_headset *ht = &headset;
unsigned long irqflags = 0;
}
#endif
+ PRINT_INFO("summer.wang headset_detect_probe");
this_pdev = pdev;
sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_AUD_EN, BIT_ANA_AUD_EN);//arm base address:0x40038800 for register accessable
}
#ifdef CONFIG_PM
-static int headset_suspend(struct platform_device *dev, pm_message_t state)
+static __maybe_unused int headset_suspend(struct platform_device *dev, pm_message_t state)
{
PRINT_INFO("suspend (det_irq = %d, but_irq = %d, plug_state_last = %d)\n",
headset.irq_detect, headset.irq_button, plug_state_last);
return 0;
}
-static int headset_resume(struct platform_device *dev)
+static __maybe_unused int headset_resume(struct platform_device *dev)
{
PRINT_INFO("resume (det_irq = %d, but_irq = %d, plug_state_last = %d)\n",
headset.irq_detect, headset.irq_button, plug_state_last);
u64 numerator = 0;
u32 denominator = 0;
u32 adc_ideal = 0;
+ u32 a, b, e;
+
if (adc_cal_headset.cal_type == SPRD_HEADSET_AUXADC_CAL_DO){
PRINT_INFO("wangzuo adc_get_ideal in\n");
- u32 a = adc_cal_headset.A;
- u32 b = adc_cal_headset.B;
- u32 e = adc_cal_headset.E;
+ a = adc_cal_headset.A;
+ b = adc_cal_headset.B;
+ e = adc_cal_headset.E;
if (9*adc_mic + b < 10*a){
return adc_mic;