"@
l<wd>z%U1%X1 %0,%1
rldicl %0,%1,0,<dbits>"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn "*zero_extend<mode>di2_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
rldicl. %2,%1,0,<dbits>
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
"@
rldicl. %0,%1,0,<dbits>
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
mtvsrwz %x0,%1
lfiwzx %0,%y1
lxsiwzx %x0,%y1"
- [(set_attr "type" "load,*,mffgpr,fpload,fpload")])
+ [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
(define_insn "extendqidi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
"@
lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
lhz%U1%X1 %0,%1
rlwinm %0,%1,0,0xffff"
- [(set_attr "type" "load,*")])
+ [(set_attr "type" "load,shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
rlwinm %0,%1,0,%m2,%M2
andi. %0,%1,%b2
andis. %0,%1,%u2"
- [(set_attr "type" "*,*,logical,logical")
+ [(set_attr "type" "*,shift,logical,logical")
(set_attr "dot" "no,no,yes,yes")])
(define_insn "andsi3_nomc"
"!rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2")
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "logical,shift")])
(define_insn "andsi3_internal0_nomc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
"!rs6000_gen_cell_microcode"
"@
and %0,%1,%2
- rlwinm %0,%1,0,%m2,%M2")
+ rlwinm %0,%1,0,%m2,%M2"
+ [(set_attr "type" "logical,shift")])
;; Note to set cr's other than cr0 we do the and immediate and then
else
operands[3] = GEN_INT (start + size);
return \"rlwinm %0,%1,%3,%s2,31\";
-}")
+}"
+ [(set_attr "type" "shift")])
(define_insn "*extzvsi_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
operands[3] = GEN_INT (start + size);
operands[2] = GEN_INT (64 - size);
return \"rldicl %0,%1,%3,%2\";
-}")
+}"
+ [(set_attr "type" "shift")])
(define_insn "*extzvdi_internal1"
[(set (match_operand:CC 0 "gpc_reg_operand" "=x")
operands[2] = GEN_INT (64 - size);
return \"rldicl. %4,%1,%3,%2\";
}"
- [(set_attr "type" "compare")])
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")])
(define_insn "*extzvdi_internal2"
[(set (match_operand:CC 4 "gpc_reg_operand" "=x")
operands[2] = GEN_INT (64 - size);
return \"rldicl. %0,%1,%3,%2\";
}"
- [(set_attr "type" "compare")])
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")])
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
"@
rlwnm %0,%1,%2,0xffffffff
rlwinm %0,%1,%h2,0xffffffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_64"
"@
rlwnm %0,%1,%2,0xffffffff
rlwinm %0,%1,%h2,0xffffffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal2"
"@
rlwnm %0,%1,%2,%m3,%M3
rlwinm %0,%1,%h2,%m3,%M3"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal5"
[(set (attr "cell_micro")
(if_then_else (match_operand:SI 2 "const_int_operand" "")
(const_string "not")
- (const_string "always")))])
+ (const_string "always")))
+ (set_attr "type" "shift")])
(define_insn "*rotlsi3_internal7be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
[(set (attr "cell_micro")
(if_then_else (match_operand:SI 2 "const_int_operand" "")
(const_string "not")
- (const_string "always")))])
+ (const_string "always")))
+ (set_attr "type" "shift")])
(define_insn "*rotlsi3_internal8le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
"@
rlwnm %0,%1,%2,0xffff
rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal10be"
"@
rlwnm %0,%1,%2,0xffff
rlwinm %0,%1,%h2,0xffff"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotlsi3_internal11le"
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "n")))]
"includes_lshift_p (operands[2], operands[3])"
- "rlwinm %0,%1,%h2,%m3,%M3")
+ "rlwinm %0,%1,%h2,%m3,%M3"
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "n")))]
"includes_rshift_p (operands[2], operands[3])"
- "rlwinm %0,%1,%s2,%m3,%M3")
+ "rlwinm %0,%1,%s2,%m3,%M3"
+ [(set_attr "type" "shift")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff")
+ "rlwinm %0,%1,%s2,0xff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal1be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 3)))]
"BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff")
+ "rlwinm %0,%1,%s2,0xff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal2le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff")
+ "rlwinm %0,%1,%s2,0xffff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal4be"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 2)))]
"BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff")
+ "rlwinm %0,%1,%s2,0xffff"
+ [(set_attr "type" "shift")])
(define_insn "*lshiftrt_internal5le"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
rldcl %0,%1,%2,0
rldicl %0,%1,%H2,0"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal2"
"@
rldc%B3 %0,%1,%2,%S3
rldic%B3 %0,%1,%H2,%S3"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal5"
"@
rldcl %0,%1,%2,56
rldicl %0,%1,%H2,56"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal7be"
"@
rldcl %0,%1,%2,56
rldicl %0,%1,%H2,56"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal8le"
"@
rldcl %0,%1,%2,48
rldicl %0,%1,%H2,48"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal10be"
"@
rldcl %0,%1,%2,48
rldicl %0,%1,%H2,48"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal11le"
"@
rldcl %0,%1,%2,32
rldicl %0,%1,%H2,32"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal13be"
"@
rldcl %0,%1,%2,32
rldicl %0,%1,%H2,32"
- [(set_attr "type" "shift,integer")
+ [(set_attr "type" "shift")
(set_attr "var_shift" "yes,no")])
(define_insn "*rotldi3_internal14le"
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "const_int_operand" "n")))]
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
- "rldic %0,%1,%H2,%W3")
+ "rldic %0,%1,%H2,%W3"
+ [(set_attr "type" "shift")])
(define_insn "ashldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
rldic. %4,%1,%H2,%W3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
"@
rldic. %0,%1,%H2,%W3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:DI 3 "mask64_operand" "n")))]
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
- "rldicr %0,%1,%H2,%S3")
+ "rldicr %0,%1,%H2,%S3"
+ [(set_attr "type" "shift")])
(define_insn "ashldi3_internal8"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
rldicr. %4,%1,%H2,%S3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
"@
rldicr. %0,%1,%H2,%S3
#"
- [(set_attr "type" "compare")
+ [(set_attr "type" "shift")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
andi. %0,%1,%b2
andis. %0,%1,%u2
#"
- [(set_attr "type" "*,*,*,logical,logical,*")
+ [(set_attr "type" "*,shift,shift,logical,logical,*")
(set_attr "dot" "no,no,no,yes,yes,no")
(set_attr "length" "4,4,4,4,4,8")])
rldic%B2 %0,%1,0,%S2
rlwinm %0,%1,0,%m2,%M2
#"
- [(set_attr "length" "4,4,4,8")])
+ [(set_attr "type" "*,shift,shift,*")
+ (set_attr "length" "4,4,4,8")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
#
#
#"
- [(set_attr "type" "logical,compare,shift,logical,\
+ [(set_attr "type" "logical,shift,shift,logical,\
logical,compare,compare,compare,compare,compare,\
compare,compare")
(set_attr "dot" "yes")
#
#
#"
- [(set_attr "type" "logical,compare,shift,logical,\
+ [(set_attr "type" "logical,shift,shift,logical,\
logical,compare,compare,compare,compare,compare,\
compare,compare")
(set_attr "dot" "yes")