agx: Handle load_instance_id
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Sat, 24 Jul 2021 19:12:18 +0000 (15:12 -0400)
committerAlyssa Rosenzweig <alyssa@rosenzweig.io>
Sat, 24 Jul 2021 19:12:18 +0000 (15:12 -0400)
Preloaded into r6, as predicted.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>

src/asahi/compiler/agx_compile.c
src/asahi/compiler/agx_register_allocate.c

index 368488b..f956326 100644 (file)
@@ -388,6 +388,9 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr *instr)
   case nir_intrinsic_load_vertex_id:
      return agx_mov_to(b, dst, agx_abs(agx_register(10, AGX_SIZE_32)));
 
+  case nir_intrinsic_load_instance_id:
+     return agx_mov_to(b, dst, agx_abs(agx_register(12, AGX_SIZE_32)));
+
   case nir_intrinsic_load_blend_const_color_r_float: return agx_blend_const(b, dst, 0);
   case nir_intrinsic_load_blend_const_color_g_float: return agx_blend_const(b, dst, 1);
   case nir_intrinsic_load_blend_const_color_b_float: return agx_blend_const(b, dst, 2);
index c8826de..e282ed4 100644 (file)
@@ -103,6 +103,8 @@ agx_ra_assign_local(agx_block *block, uint8_t *ssa_to_reg, uint8_t *ncomps, unsi
    BITSET_SET(used_regs, 0); // control flow writes r0l
    BITSET_SET(used_regs, 5*2); // TODO: precolouring, don't overwrite vertex ID
    BITSET_SET(used_regs, (5*2 + 1));
+   BITSET_SET(used_regs, (6*2 + 0));
+   BITSET_SET(used_regs, (6*2 + 1));
 
    agx_foreach_instr_in_block(block, I) {
       /* First, free killed sources */