arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
authorAswath Govindraju <a-govindraju@ti.com>
Fri, 28 Jan 2022 08:11:39 +0000 (13:41 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 16:00:03 +0000 (11:00 -0500)
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
arch/arm/dts/k3-j721e-r5-common-proc-board.dts

index 3ca9b5c..938e978 100644 (file)
 &usb_serdes_mux {
        u-boot,mux-autoprobe;
 };
+
+&serdes0 {
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+};
+
+&serdes0_pcie_link {
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
+};
index 4b2362a..8299463 100644 (file)
@@ -8,6 +8,7 @@
 #include "k3-j721e-som-p0.dtsi"
 #include "k3-j721e-ddr-evm-lp4-4266.dtsi"
 #include "k3-j721e-ddr.dtsi"
+#include <dt-bindings/phy/phy-cadence.h>
 
 / {
        aliases {
 &mcu_udmap {
        ti,sci = <&dm_tifs>;
 };
+
+&wiz0_pll1_refclk {
+       assigned-clocks = <&wiz0_pll1_refclk>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+       assigned-clocks = <&wiz0_refclk_dig>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes0 {
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
+
+       serdes0_pcie_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>;
+       };
+};