tests/amdgpu: add sdma corrupted header hang test

Issue corrupted header for sdma to trigger SDMA hang test.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 7f3aee4..406d07a 100644 (file)
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -549,6 +549,10 @@ static void amdgpu_disable_suites()
                                "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
                        fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
 
+       if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
+                       "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", CU_FALSE))
+               fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
+
        if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE))
                fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
 

diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index 2435751..de0e6e0 100644 (file)
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -124,6 +124,7 @@ static void amdgpu_dispatch_hang_slow_gfx(void);
 static void amdgpu_dispatch_hang_slow_compute(void);
 static void amdgpu_draw_hang_gfx(void);
 static void amdgpu_draw_hang_slow_gfx(void);
+static void amdgpu_hang_sdma(void);
 
 CU_BOOL suite_deadlock_tests_enable(void)
 {
@@ -208,6 +209,7 @@ CU_TestInfo deadlock_tests[] = {
        { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute },
        { "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx },
        { "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx },
+       { "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", amdgpu_hang_sdma },
        CU_TEST_INFO_NULL,
 };
 
@@ -533,3 +535,124 @@ static void amdgpu_draw_hang_slow_gfx(void)
 {
        amdgpu_test_draw_hang_slow_helper(device_handle);
 }
+
+static void amdgpu_hang_sdma(void)
+{
+       const int sdma_write_length = 1024;
+       amdgpu_context_handle context_handle;
+       amdgpu_bo_handle ib_result_handle;
+       amdgpu_bo_handle bo1, bo2;
+       amdgpu_bo_handle resources[3];
+       amdgpu_bo_list_handle bo_list;
+       void *ib_result_cpu;
+       struct amdgpu_cs_ib_info ib_info;
+       struct amdgpu_cs_request ibs_request;
+       struct amdgpu_cs_fence fence_status;
+       uint64_t bo1_mc, bo2_mc;
+       uint64_t ib_result_mc_address;
+       volatile unsigned char *bo1_cpu, *bo2_cpu;
+       amdgpu_va_handle bo1_va_handle, bo2_va_handle;
+       amdgpu_va_handle va_handle;
+       struct drm_amdgpu_info_hw_ip hw_ip_info;
+       int i, r;
+       uint32_t expired;
+
+       r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &hw_ip_info);
+       CU_ASSERT_EQUAL(r, 0);
+
+       r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+       CU_ASSERT_EQUAL(r, 0);
+
+       r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+                                   AMDGPU_GEM_DOMAIN_GTT, 0,
+                                   &ib_result_handle, &ib_result_cpu,
+                                   &ib_result_mc_address, &va_handle);
+       CU_ASSERT_EQUAL(r, 0);
+
+       r = amdgpu_bo_alloc_and_map(device_handle,
+                                   sdma_write_length, 4096,
+                                   AMDGPU_GEM_DOMAIN_GTT,
+                                   0, &bo1,
+                                   (void**)&bo1_cpu, &bo1_mc,
+                                   &bo1_va_handle);
+       CU_ASSERT_EQUAL(r, 0);
+
+       /* set bo1 */
+       memset((void*)bo1_cpu, 0xaa, sdma_write_length);
+
+       /* allocate UC bo2 for sDMA use */
+       r = amdgpu_bo_alloc_and_map(device_handle,
+                                   sdma_write_length, 4096,
+                                   AMDGPU_GEM_DOMAIN_GTT,
+                                   0, &bo2,
+                                   (void**)&bo2_cpu, &bo2_mc,
+                                   &bo2_va_handle);
+       CU_ASSERT_EQUAL(r, 0);
+
+       /* clear bo2 */
+       memset((void*)bo2_cpu, 0, sdma_write_length);
+
+       resources[0] = bo1;
+       resources[1] = bo2;
+       resources[2] = ib_result_handle;
+       r = amdgpu_bo_list_create(device_handle, 3,
+                                 resources, NULL, &bo_list);
+
+       /* fulfill PM4: with bad copy linear header */
+       ptr = ib_result_cpu;
+       i = 0;
+       ptr[i++] = 0x23decd3d;
+       ptr[i++] = sdma_write_length - 1;
+       ptr[i++] = 0;
+       ptr[i++] = 0xffffffff & bo1_mc;
+       ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
+       ptr[i++] = 0xffffffff & bo2_mc;
+       ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
+
+       /* exec command */
+       memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
+       ib_info.ib_mc_address = ib_result_mc_address;
+       ib_info.size = i;
+
+       memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
+       ibs_request.ip_type = AMDGPU_HW_IP_DMA;
+       ibs_request.ring = 0;
+       ibs_request.number_of_ibs = 1;
+       ibs_request.ibs = &ib_info;
+       ibs_request.resources = bo_list;
+       ibs_request.fence_info.handle = NULL;
+
+       r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
+       CU_ASSERT_EQUAL(r, 0);
+
+       memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+       fence_status.context = context_handle;
+       fence_status.ip_type = AMDGPU_HW_IP_DMA;
+       fence_status.ip_instance = 0;
+       fence_status.ring = 0;
+       fence_status.fence = ibs_request.seq_no;
+
+       r = amdgpu_cs_query_fence_status(&fence_status,
+                                        AMDGPU_TIMEOUT_INFINITE,
+                                        0, &expired);
+       CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
+
+       r = amdgpu_bo_list_destroy(bo_list);
+       CU_ASSERT_EQUAL(r, 0);
+
+       r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+                                    ib_result_mc_address, 4096);
+       CU_ASSERT_EQUAL(r, 0);
+
+       r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
+                                    sdma_write_length);
+       CU_ASSERT_EQUAL(r, 0);
+
+       r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
+                                    sdma_write_length);
+       CU_ASSERT_EQUAL(r, 0);
+
+       /* end of test */
+       r = amdgpu_cs_ctx_free(context_handle);
+       CU_ASSERT_EQUAL(r, 0);
+}