arm64: dts: imx8mm: Deduplicate PCIe clock-names property

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index 03266bd..f3cb7e2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -241,9 +241,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk_gated>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
index 24f61db..b337af0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
@@ -904,9 +904,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcieclk 0>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index e0b604a..0ce3005 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -360,9 +360,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
index 44e87b1..299752a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
@@ -210,9 +210,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
-                <&clk IMX8MM_CLK_PCIE1_AUX>;
-       clock-names = "pcie", "pcie_bus", "pcie_aux";
        fsl,max-link-speed = <1>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index 4a3df2b..266129b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@ -175,9 +175,6 @@
        assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
                                 <&clk IMX8MM_SYS_PLL2_250M>;
        assigned-clock-rates = <10000000>, <250000000>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&clk IMX8MM_CLK_PCIE1_PHY>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie>;
        reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
index a0aeac6..156d793 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -79,9 +79,8 @@
 
 &pcie0 {
        reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-               <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                                <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
index c557dbf..0ce60ad 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -120,9 +120,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
index 41d0de6..570992a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -142,9 +142,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
index 244ef8d..47ba0be 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -162,9 +162,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 750a1f0..2bd117c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -702,9 +702,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index 32872b0..feae219 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -623,9 +623,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
index 8ce5622..e7c79a8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
@@ -557,9 +557,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
index eceed98..93088fa 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
@@ -618,9 +618,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&pcie0_refclk>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
+       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+                <&clk IMX8MM_CLK_PCIE1_AUX>;
        assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
                          <&clk IMX8MM_CLK_PCIE1_CTRL>;
        assigned-clock-rates = <10000000>, <250000000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 7e8b3b0..5b2493b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -657,10 +657,6 @@
        assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
                                 <&clk IMX8MM_SYS_PLL2_250M>;
        assigned-clock-rates = <10000000>, <250000000>;
-       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
-                <&clk IMX8MM_CLK_PCIE1_AUX>,
-                <&clk IMX8MM_CLK_PCIE1_PHY>;
-       clock-names = "pcie", "pcie_aux", "pcie_bus";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
        /* PCIE_1_RESET# (SODIMM 244) */

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 04cf2c3..31f4548 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1302,6 +1302,10 @@
                                        <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
                        fsl,max-link-speed = <2>;
                        linux,pci-domain = <0>;
+                       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+                                <&clk IMX8MM_CLK_PCIE1_PHY>,
+                                <&clk IMX8MM_CLK_PCIE1_AUX>;
+                       clock-names = "pcie", "pcie_bus", "pcie_aux";
                        power-domains = <&pgc_pcie>;
                        resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
                                 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;