drm/amd/powerplay: add profiling mode in dpm level
authorRex Zhu <Rex.Zhu@amd.com>
Fri, 23 Dec 2016 07:24:37 +0000 (15:24 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 27 Jan 2017 16:12:57 +0000 (11:12 -0500)
In some case, App need to run under max stable clock.
so export profiling mode: GFX CG was disabled.
and user can select the max stable clock of the device.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

index ccf50b8..0345fbb 100644 (file)
@@ -124,6 +124,7 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
                        (level & AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
                        (level & AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
                        (level & AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
+                       (level & AMD_DPM_FORCED_LEVEL_PROFILING) ? "profiling" :
                        "unknown"));
 }
 
@@ -135,6 +136,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
        struct drm_device *ddev = dev_get_drvdata(dev);
        struct amdgpu_device *adev = ddev->dev_private;
        enum amd_dpm_forced_level level;
+       enum amd_dpm_forced_level current_level;
        int ret = 0;
 
        /* Can't force performance level when the card is off */
@@ -142,6 +144,8 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
                return -EINVAL;
 
+       current_level = amdgpu_dpm_get_performance_level(adev);
+
        if (strncmp("low", buf, strlen("low")) == 0) {
                level = AMD_DPM_FORCED_LEVEL_LOW;
        } else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -150,11 +154,24 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
                level = AMD_DPM_FORCED_LEVEL_AUTO;
        } else if (strncmp("manual", buf, strlen("manual")) == 0) {
                level = AMD_DPM_FORCED_LEVEL_MANUAL;
+       } else if (strncmp("profile", buf, strlen("profile")) == 0) {
+               level = AMD_DPM_FORCED_LEVEL_PROFILING;
        } else {
                count = -EINVAL;
                goto fail;
        }
 
+       if (current_level == level)
+               return 0;
+
+       if (level == AMD_DPM_FORCED_LEVEL_PROFILING)
+               amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
+                                               AMD_CG_STATE_UNGATE);
+       else if (level != AMD_DPM_FORCED_LEVEL_PROFILING &&
+                       current_level == AMD_DPM_FORCED_LEVEL_PROFILING)
+               amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
+                                               AMD_CG_STATE_GATE);
+
        if (adev->pp_enabled)
                amdgpu_dpm_force_performance_level(adev, level);
        else {
index ab7d2bb..9a544ad 100644 (file)
@@ -6571,8 +6571,8 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
 {
        struct ci_power_info *pi = ci_get_pi(adev);
 
-       if (adev->pm.dpm.forced_level
-                       != AMD_DPM_FORCED_LEVEL_MANUAL)
+       if (!(adev->pm.dpm.forced_level &
+               (AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
                return -EINVAL;
 
        switch (type) {
index c92532c..92138a9 100644 (file)
@@ -85,6 +85,7 @@ enum amd_dpm_forced_level {
        AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
        AMD_DPM_FORCED_LEVEL_LOW = 0x4,
        AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
+       AMD_DPM_FORCED_LEVEL_PROFILING = 0x10,
 };
 
 enum amd_powergating_state {
index 9bb94af..f4ff236 100644 (file)
@@ -1644,7 +1644,8 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
                enum pp_clock_type type, uint32_t mask)
 {
-       if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+       if (!(hwmgr->dpm_level &
+               (AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
                return -EINVAL;
 
        switch (type) {
index 9232c11..8bd1e96 100644 (file)
@@ -4031,7 +4031,8 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 {
        struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
-       if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+       if (!(hwmgr->dpm_level &
+               (AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
                return -EINVAL;
 
        switch (type) {