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sse.md (define_mode_iterator VF2_AVX512VL): New.
authorAlexander Ivchenko <alexander.ivchenko@intel.com>
Mon, 18 Aug 2014 10:59:46 +0000 (10:59 +0000)
committerKirill Yukhin <kyukhin@gcc.gnu.org>
Mon, 18 Aug 2014 10:59:46 +0000 (10:59 +0000)
gcc/
* config/i386/sse.md
(define_mode_iterator VF2_AVX512VL): New.
(define_mode_attr sseintvecmode2): New.
(define_insn "ufix_truncv2dfv2si2<mask_name>"): Add masking.
(define_insn "fix_truncv4dfv4si2<mask_name>"): New.
(define_insn "ufix_truncv4dfv4si2<mask_name>"): Ditto.
(define_insn
"<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"):
Ditto.
(define_insn "fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"):
Ditto.
(define_insn "ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"):
Ditto.

Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
From-SVN: r214090

gcc/ChangeLog patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 687e4b6..5076b9d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -7,6 +7,29 @@
            Kirill Yukhin  <kirill.yukhin@intel.com>
            Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 
+       * config/i386/sse.md
+       (define_mode_iterator VF2_AVX512VL): New.
+       (define_mode_attr sseintvecmode2): New.
+       (define_insn "ufix_truncv2dfv2si2<mask_name>"): Add masking.
+       (define_insn "fix_truncv4dfv4si2<mask_name>"): New.
+       (define_insn "ufix_truncv4dfv4si2<mask_name>"): Ditto.
+       (define_insn
+       "<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"):
+       Ditto.
+       (define_insn "fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"):
+       Ditto.
+       (define_insn "ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"):
+       Ditto.
+
+2014-08-18  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
        * config/i386/i386.md
        (define_insn "*movoi_internal_avx"): Add evex version.
        (define_insn "*movti_internal"): Ditto.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 80dbf17..141c431 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -228,6 +228,9 @@
 (define_mode_iterator VF_512
   [V16SF V8DF])
 
+(define_mode_iterator VF2_AVX512VL
+  [V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
+
 ;; All vector integer modes
 (define_mode_iterator VI
   [(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")
@@ -523,6 +526,10 @@
    (V32HI "V32HI") (V64QI "V64QI")
    (V32QI "V32QI") (V16QI "V16QI")])
 
+(define_mode_attr sseintvecmode2
+  [(V8DF "XI") (V4DF "OI") (V2DF "TI")
+   (V8SF "OI") (V4SF "TI")])
+
 (define_mode_attr sseintvecmodelower
   [(V16SF "v16si") (V8DF "v8di")
    (V8SF "v8si") (V4DF "v4di")
@@ -4235,15 +4242,67 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "OI")])
 
-(define_insn "fix_truncv4dfv4si2"
-  [(set (match_operand:V4SI 0 "register_operand" "=x")
-       (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
-  "TARGET_AVX"
-  "vcvttpd2dq{y}\t{%1, %0|%0, %1}"
+(define_insn "ufix_truncv2dfv2si2<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+       (vec_concat:V4SI
+         (unsigned_fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
+         (const_vector:V2SI [(const_int 0) (const_int 0)])))]
+  "TARGET_AVX512VL"
+  "vcvttpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "TI")])
+
+(define_insn "fix_truncv4dfv4si2<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+       (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
+  "TARGET_AVX || (TARGET_AVX512VL && TARGET_AVX512F)"
+  "vcvttpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "maybe_evex")
+   (set_attr "mode" "OI")])
+
+(define_insn "ufix_truncv4dfv4si2<mask_name>"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+       (unsigned_fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
+  "TARGET_AVX512VL && TARGET_AVX512F"
+  "vcvttpd2udq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "OI")])
 
+(define_insn "<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"
+  [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
+       (any_fix:<sseintvecmode>
+         (match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
+  "TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
+  "vcvttpd2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseintvecmode2>")])
+
+(define_insn "fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"
+  [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
+       (unspec:<sseintvecmode>
+         [(match_operand:VF2_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")]
+         UNSPEC_FIX_NOTRUNC))]
+  "TARGET_AVX512DQ && <round_mode512bit_condition>"
+  "vcvtpd2qq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseintvecmode2>")])
+
+(define_insn "ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"
+  [(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
+       (unspec:<sseintvecmode>
+         [(match_operand:VF2_AVX512VL 1 "nonimmediate_operand" "<round_constraint>")]
+         UNSPEC_UNSIGNED_FIX_NOTRUNC))]
+  "TARGET_AVX512DQ && <round_mode512bit_condition>"
+  "vcvtpd2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
+  [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseintvecmode2>")])
+
 (define_expand "avx_cvttpd2dq256_2"
   [(set (match_operand:V8SI 0 "register_operand")
        (vec_concat:V8SI
Domain: System / Toolchain;