case SImode:
if (TARGET_CONST16)
return CONSTANT_P (op);
- /* fall through */
+ /* Fall through. */
case HImode:
case QImode:
{
rtx offset;
- /* only handle (PLUS (SYM, OFFSET)) form */
+ /* Only handle (PLUS (SYM, OFFSET)) form. */
addr = XEXP (addr, 0);
if (GET_CODE (addr) != PLUS)
return FALSE;
- /* make sure the address is word aligned */
+ /* Make sure the address is word aligned. */
offset = XEXP (addr, 1);
if ((GET_CODE (offset) != CONST_INT)
|| ((INTVAL (offset) & 3) != 0))
rtx temp = gen_reg_rtx (SImode);
rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
- /* generate paradoxical subregs as needed so that the modes match */
+ /* Generate paradoxical subregs as needed so that the modes match. */
src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
if (boolean_operator (cmp, VOIDmode))
{
- /* swap the operands to make const0 second */
+ /* Swap the operands to make const0 second. */
if (op0 == const0_rtx)
{
op0 = op1;
op1 = const0_rtx;
}
- /* if not comparing against zero, emit a comparison (subtract) */
+ /* If not comparing against zero, emit a comparison (subtract). */
if (op1 != const0_rtx)
{
op0 = expand_binop (SImode, sub_optab, op0, op1,
}
else if (branch_operator (cmp, VOIDmode))
{
- /* swap the operands to make const0 second */
+ /* Swap the operands to make const0 second. */
if (op0 == const0_rtx)
{
op0 = op1;
int align = XINT (operands[3], 0);
int num_pieces, move_ratio;
- /* If this is not a fixed size move, just call memcpy */
+ /* If this is not a fixed size move, just call memcpy. */
if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
return 0;
- /* Anything to move? */
+ /* Anything to move? */
if (bytes <= 0)
return 1;
if (align > MOVE_MAX)
align = MOVE_MAX;
- /* decide whether to expand inline based on the optimization level */
+ /* Decide whether to expand inline based on the optimization level. */
move_ratio = 4;
if (optimize > 2)
move_ratio = LARGEST_MOVE_RATIO;
- num_pieces = (bytes / align) + (bytes % align); /* close enough anyway */
+ num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
if (num_pieces >= move_ratio)
return 0;
- /* make sure the memory addresses are valid */
+ /* Make sure the memory addresses are valid. */
operands[0] = validize_mem (dest);
operands[1] = validize_mem (src);
}
-/* Emit a sequence of instructions to implement a block move, trying
- to hide load delay slots as much as possible. Load N values into
- temporary registers, store those N values, and repeat until the
- complete block has been moved. N=delay_slots+1 */
+/* Emit a sequence of instructions to implement a block move, trying
+ to hide load delay slots as much as possible. Load N values into
+ temporary registers, store those N values, and repeat until the
+ complete block has been moved. N=delay_slots+1. */
struct meminsnbuf
{
if (bytes < item_size)
{
- /* find a smaller item_size which we can load & store */
+ /* Find a smaller item_size which we can load & store. */
item_size = bytes;
mode = xtensa_find_mode_for_size (item_size);
item_size = GET_MODE_SIZE (mode);
stname = xtensa_st_opcodes[(int) mode];
}
- /* record the load instruction opcode and operands */
+ /* Record the load instruction opcode and operands. */
addr = plus_constant (from_addr, offset);
mem = gen_rtx_MEM (mode, addr);
if (! memory_address_p (mode, addr))
ldinsns[n].operands[1] = mem;
sprintf (ldinsns[n].template, "%s\t%%0, %%1", ldname);
- /* record the store instruction opcode and operands */
+ /* Record the store instruction opcode and operands. */
addr = plus_constant (to_addr, offset);
mem = gen_rtx_MEM (mode, addr);
if (! memory_address_p (mode, addr))
bytes -= item_size;
}
- /* now output the loads followed by the stores */
+ /* Now output the loads followed by the stores. */
for (n = 0; n < chunk_size; n++)
output_asm_insn (ldinsns[n].template, ldinsns[n].operands);
for (n = 0; n < chunk_size; n++)
{
mode = VOIDmode;
- /* find mode closest to but not bigger than item_size */
+ /* Find mode closest to but not bigger than item_size. */
for (tmode = GET_CLASS_NARROWEST_MODE (MODE_INT);
tmode != VOIDmode; tmode = GET_MODE_WIDER_MODE (tmode))
if (GET_MODE_SIZE (tmode) <= item_size)
&& xtensa_st_opcodes[(int) mode])
break;
- /* cannot load & store this mode; try something smaller */
+ /* Cannot load & store this mode; try something smaller. */
item_size -= 1;
}
rtx goto_handler = operands[1];
rtx containing_fp = operands[3];
- /* generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
- is too big to generate in-line */
+ /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
+ is too big to generate in-line. */
if (GET_CODE (containing_fp) != REG)
containing_fp = force_reg (Pmode, containing_fp);
if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
error ("boolean registers required for the floating-point option");
- /* set up the tables of ld/st opcode names for block moves */
+ /* Set up the tables of ld/st opcode names for block moves. */
xtensa_ld_opcodes[(int) SImode] = "l32i";
xtensa_ld_opcodes[(int) HImode] = "l16ui";
xtensa_ld_opcodes[(int) QImode] = "l8ui";
if (gp_left == 0)
return const0_rtx;
- /* allocate the general-purpose register space */
+ /* Allocate the general-purpose register space. */
gp_regs = assign_stack_local
(BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
set_mem_alias_set (gp_regs, get_varargs_alias_set ());
int i, num_arg_regs;
int nxt = 0;
- /* use the AR registers in increasing order (skipping a0 and a1)
- but save the incoming argument registers for a last resort */
+ /* Use the AR registers in increasing order (skipping a0 and a1)
+ but save the incoming argument registers for a last resort. */
num_arg_regs = current_function_args_info.arg_words;
if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
num_arg_regs = MAX_ARGS_IN_REGISTERS;
for (i = 0; i < num_arg_regs; i++)
reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
- /* list the coprocessor registers in order */
+ /* List the coprocessor registers in order. */
for (i = 0; i < BR_REG_NUM; i++)
reg_alloc_order[nxt++] = BR_REG_FIRST + i;
- /* list the FP registers in order for now */
+ /* List the FP registers in order for now. */
for (i = 0; i < 16; i++)
reg_alloc_order[nxt++] = FP_REG_FIRST + i;
case LSHIFTRT:
case ROTATE:
case ROTATERT:
- /* no way to tell if X is the 2nd operand so be conservative */
+ /* No way to tell if X is the 2nd operand so be conservative. */
default: break;
}
if (xtensa_simm12b (INTVAL (x)))
return true;
}
}
- /* fall through */
+ /* Fall through. */
case UDIV:
case UMOD:
in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-/* Define this if most significant byte of a word is the lowest numbered. */
+/* Define this if most significant byte of a word is the lowest numbered. */
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-/* Define this if most significant word of a multiword number is the lowest. */
+/* Define this if most significant word of a multiword number is the lowest. */
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#define MAX_BITS_PER_WORD 32
#define FIRST_PSEUDO_REGISTER 36
-/* Return the stabs register number to use for REGNO. */
+/* Return the stabs register number to use for REGNO. */
#define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator. */
+ and are not available for the register allocator. */
#define FIXED_REGISTERS \
{ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
giving preference to call-used registers. To minimize window
overflows for the AR registers, we want to give preference to the
lower-numbered AR registers. For other register files, which are
- not windowed, we still prefer call-used registers, if there are any. */
+ not windowed, we still prefer call-used registers, if there are any. */
extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
#define LEAF_REGISTERS xtensa_leaf_regs
/* For Xtensa, no remapping is necessary, but this macro must be
- defined if LEAF_REGISTERS is defined. */
+ defined if LEAF_REGISTERS is defined. */
#define LEAF_REG_REMAP(REGNO) (REGNO)
-/* this must be declared if LEAF_REGISTERS is set */
+/* This must be declared if LEAF_REGISTERS is set. */
extern int leaf_function;
-/* Internal macros to classify a register number. */
+/* Internal macros to classify a register number. */
/* 16 address registers + fake registers */
#define GP_REG_FIRST 0
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode
- MODE. */
+ MODE. */
extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
/* The register number of the frame pointer register, which is used to
access automatic variables in the stack frame. For Xtensa, this
register never appears in the output. It is always eliminated to
- either the stack pointer or the hard frame pointer. */
+ either the stack pointer or the hard frame pointer. */
#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
/* Value should be nonzero if functions must have frame pointers.
/* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
16 AR registers may be explicitly used in the RTL, as either
- incoming or outgoing arguments. */
+ incoming or outgoing arguments. */
#define SMALL_REGISTER_CLASSES 1
the meantime, the constraints are checked and none match. The
solution seems to be to simply skip the offset check here. The
address will be checked anyway because of the code in
- GO_IF_LEGITIMATE_ADDRESS. */
+ GO_IF_LEGITIMATE_ADDRESS. */
#define EXTRA_CONSTRAINT(OP, CODE) \
((GET_CODE (OP) != MEM) ? \
/* Define how to find the value returned by a library function
assuming the value has mode MODE. Because we have defined
PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
- PROMOTE_MODE. */
+ PROMOTE_MODE. */
#define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
be recognized by this macro. If the machine has register windows,
so that the caller and the called function use different registers
for the return value, this macro should recognize only the caller's
- register numbers. */
+ register numbers. */
#define FUNCTION_VALUE_REGNO_P(N) \
((N) == GP_RETURN)
does *not* include implicit arguments such as the static chain and
the structure-value address. On many machines, no registers can be
used for this purpose since all function arguments are pushed on
- the stack. */
+ the stack. */
#define FUNCTION_ARG_REGNO_P(N) \
((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
during the scan of that argument list. This data type should
hold all necessary information about the function itself
and about the args processed so far, enough to enable macros
- such as FUNCTION_ARG to determine where the next arg should go. */
+ such as FUNCTION_ARG to determine where the next arg should go. */
typedef struct xtensa_args {
int arg_words; /* # total words the arguments take */
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
- For a library call, FNTYPE is 0. */
+ For a library call, FNTYPE is 0. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME)
This differs from the default in that it does not check if the padding
and mode of the type are such that a copy into a register would put it
- into the wrong part of the register. */
+ into the wrong part of the register. */
#define MUST_PASS_IN_STACK(MODE, TYPE) \
((TYPE) != 0 \
values contain window size information in the two most significant
bits; we assume that _mcount will mask off those bits. The call to
_mcount uses a window size of 8 to make sure that it doesn't clobber
- any incoming argument values. */
+ any incoming argument values. */
#define NO_PROFILE_COUNTERS 1
from the entry instruction at the target and the current frame is
adjusted to match. The trampoline then transfers control to the
instruction following the entry at the target. Note: this assumes
- that the target begins with an entry instruction. */
+ that the target begins with an entry instruction. */
/* minimum frame = reg save area (4 words) plus static chain (1 word)
and the total number of words must be a multiple of 128 bits */
code for a call to '__builtin_saveregs'. This code will be moved
to the very beginning of the function, before any parameter access
are made. The return value of this function should be an RTX that
- contains the value to use as the return of '__builtin_saveregs'. */
+ contains the value to use as the return of '__builtin_saveregs'. */
#define EXPAND_BUILTIN_SAVEREGS \
xtensa_builtin_saveregs
specify whether to start from the stack pointer or frame pointer. That
would also allow us to skip the machine->accesses_prev_frame stuff that
we currently need to ensure that there is a frame pointer when these
- builtin functions are used. */
+ builtin functions are used. */
#define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
macro is used for continuing to walk back up the stack, so it must
return the stack pointer address. Thus, there is some inconsistency
here in that __builtin_frame_address will return the frame pointer
- when count == 0 and the stack pointer when count > 0. */
+ when count == 0 and the stack pointer when count > 0. */
#define DYNAMIC_CHAIN_ADDRESS(frame) \
gen_rtx (PLUS, Pmode, frame, \
gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
/* Define this if the return address of a particular stack frame is
- accessed from the frame pointer of the previous stack frame. */
+ accessed from the frame pointer of the previous stack frame. */
#define RETURN_ADDR_IN_PREVIOUS_FRAME
/* A C expression whose value is RTL representing the value of the
be either a suitable hard register or a pseudo register that has
been allocated such a hard register. The difference between an
index register and a base register is that the index register may
- be scaled. */
+ be scaled. */
#define REGNO_OK_FOR_BASE_P(NUM) \
(GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
must be controlled by `REG_OK_STRICT'. This usually requires two
variant definitions, of which `REG_OK_STRICT' controls the one
actually used. The difference between an index register and a base
- register is that the index register may be scaled. */
+ register is that the index register may be scaled. */
#ifdef REG_OK_STRICT
|| (GET_CODE (X) == CONST)))
/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
+ It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
#define LEGITIMATE_CONSTANT_P(X) 1
/* A C expression that is nonzero if X is a legitimate immediate
#define SHIFT_COUNT_TRUNCATED 1
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
- is done just by pretending it is already truncated. */
+ is done just by pretending it is already truncated. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
/* Specify the machine mode that pointers have.
/* Control the assembler format that we output. */
/* How to refer to registers in assembler output.
- This sequence is indexed by compiler's hard-register-number (see above). */
+ This sequence is indexed by compiler's hard-register-number (see above). */
#define REGISTER_NAMES \
{ \
"a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
/* If defined, a C initializer for an array of structures containing a
name and a register number. This macro defines additional names
for hard registers, thus allowing the 'asm' option in declarations
- to refer to registers using alternate names. */
+ to refer to registers using alternate names. */
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "a1", 1 + GP_REG_FIRST } \
LOCAL_LABEL_PREFIX, VALUE)
/* This is how to output an element of a case-vector that is relative.
- This is used for pc-relative code. */
+ This is used for pc-relative code. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
/* Define output to appear before the constant pool. If the function
has been assigned to a specific ELF section, or if it goes into a
unique section, set the name of that section to be the literal
- prefix. */
+ prefix. */
#define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
do { \
tree fnsection; \
goto JUMPTO; \
} while (0)
-/* How to start an assembler comment. */
+/* How to start an assembler comment. */
#define ASM_COMMENT_START "#"
/* Exception handling TODO!! */
projects / platform / upstream / gcc.git / commitdiff