driver/nand:Define MAX_BANKS same as SoC defined for IFC
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Thu, 12 Jun 2014 03:43:08 +0000 (09:13 +0530)
committerYork Sun <yorksun@freescale.com>
Tue, 22 Jul 2014 23:25:54 +0000 (16:25 -0700)
The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/mtd/nand/fsl_ifc_nand.c

index be5a16a..27f5177 100644 (file)
 #include <asm/errno.h>
 #include <fsl_ifc.h>
 
+#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
+#endif
+
 #define FSL_IFC_V1_1_0 0x01010000
-#define MAX_BANKS      4
+#define MAX_BANKS      CONFIG_SYS_FSL_IFC_BANK_COUNT
 #define ERR_BYTE       0xFF /* Value returned for read bytes
                                when read failed */
 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC