#define ARM_LOCAL_GPU_INT_ROUTING 0x0c
#define REG_FIQ_CONTROL 0x0c
-#define REG_FIQ_ENABLE 0x80
-#define REG_FIQ_DISABLE 0
+#define FIQ_CONTROL_ENABLE BIT(7)
#define NR_BANKS 3
#define IRQS_PER_BANK 32
static void armctrl_mask_irq(struct irq_data *d)
{
if (d->hwirq >= NUMBER_IRQS)
- writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
+ writel_relaxed(0, intc.base + REG_FIQ_CONTROL);
else
writel_relaxed(HWIRQ_BIT(d->hwirq),
intc.disable[HWIRQ_BANK(d->hwirq)]);
ARM_LOCAL_GPU_INT_ROUTING);
}
- writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
+ writel_relaxed(FIQ_CONTROL_ENABLE | hwirq_to_fiq(d->hwirq),
intc.base + REG_FIQ_CONTROL);
} else {
writel_relaxed(HWIRQ_BIT(d->hwirq),
{
void __iomem *base;
int irq = 0, last_irq, b, i;
+ u32 reg;
base = of_iomap(node, 0);
if (!base)
handle_level_irq);
irq_set_probe(irq);
}
+
+ reg = readl_relaxed(intc.enable[b]);
+ if (reg) {
+ writel_relaxed(reg, intc.disable[b]);
+ pr_err(FW_BUG "Bootloader left irq enabled: "
+ "bank %d irq %*pbl\n", b, IRQS_PER_BANK, ®);
+ }
+ }
+
+ reg = readl_relaxed(base + REG_FIQ_CONTROL);
+ if (reg & FIQ_CONTROL_ENABLE) {
+ writel_relaxed(0, base + REG_FIQ_CONTROL);
+ pr_err(FW_BUG "Bootloader left fiq enabled\n");
}
last_irq = irq;