int bclk; /* Desired BCLK */
int lrclk;
+ struct completion fll_lock;
int fll_src;
int fll_fref;
int fll_fout;
struct snd_soc_codec *codec = dai->codec;
struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
struct _fll_div fll_div;
+ unsigned long timeout;
int ret;
int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
+ /* This should be a massive overestimate */
+ timeout = msecs_to_jiffies(1);
+
+ wait_for_completion_timeout(&wm8962->fll_lock, timeout);
+
wm8962->fll_fref = Fref;
wm8962->fll_fout = Fout;
wm8962->fll_src = source;
active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
active &= ~mask;
+ if (active & WM8962_FLL_LOCK_EINT) {
+ dev_dbg(codec->dev, "FLL locked\n");
+ complete(&wm8962->fll_lock);
+ }
+
if (active & WM8962_FIFOS_ERR_EINT)
dev_err(codec->dev, "FIFO error\n");
wm8962->codec = codec;
INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
+ init_completion(&wm8962->fll_lock);
codec->cache_sync = 1;
codec->dapm.idle_bias_off = 1;
i2c->irq, ret);
/* Non-fatal */
} else {
- /* Enable error reporting IRQs by default */
+ /* Enable some IRQs by default */
snd_soc_update_bits(codec,
WM8962_INTERRUPT_STATUS_2_MASK,
+ WM8962_FLL_LOCK_EINT |
WM8962_TEMP_SHUT_EINT |
WM8962_FIFOS_ERR_EINT, 0);
}