PR target/21501

	* arm.c (arm_gen_constant): Sign-extend intermediate values when
	synthesizing a constant of the difference of two immediates.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@99608 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fd59b35..50a41d1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2005-05-12  Richard Earnshaw  <richard.earnshaw@arm.com>
 
+       PR target/21501
+       * arm.c (arm_gen_constant): Sign-extend intermediate values when
+       synthesizing a constant of the difference of two immediates.
+
+2005-05-12  Richard Earnshaw  <richard.earnshaw@arm.com>
+
        * arm/vfp.md (negsf2_vfp): Add alternative using integer registers.
        (negdf2_vfp): Likewise.  Convert to define_insn_and_split and split
        the alternatives using integer registers into the appropriate

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 905187a..c1d1fa8 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1920,8 +1920,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
        {
          int topshift = clear_sign_bit_copies & ~1;
 
-         temp1 = ((remainder + (0x00800000 >> topshift))
-                  & (0xff000000 >> topshift));
+         temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
+                                  & (0xff000000 >> topshift));
 
          /* If temp1 is zero, then that means the 9 most significant
             bits of remainder were 1 and we've caused it to overflow.
@@ -1930,7 +1930,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
          if (temp1 == 0 && topshift != 0)
            temp1 = 0x80000000 >> (topshift - 1);
 
-         temp2 = temp1 - remainder;
+         temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
          
          if (const_ok_for_arm (temp2))
            {