Make zero_extends explicit for common AArch64 SI mode patterns

From-SVN: r194649

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e7a4b7..29cab03 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,36 @@
+2012-12-20  Ian Bolton  <ian.bolton@arm.com>
+
+       * gcc/config/aarch64/aarch64.md
+       (*addsi3_aarch64_uxtw): New pattern.
+       (*addsi3_compare0_uxtw): New pattern.
+       (*add_<shift>_si_uxtw): New pattern.
+       (*add_<optab><SHORT:mode>_si_uxtw): New pattern.
+       (*add_<optab><SHORT:mode>_shft_si_uxtw): New pattern.
+       (*add_<optab><SHORT:mode>_mult_si_uxtw): New pattern.
+       (*add_<optab>si_multp2_uxtw): New pattern.
+       (*addsi3_carryin_uxtw): New pattern.
+       (*addsi3_carryin_alt1_uxtw): New pattern.
+       (*addsi3_carryin_alt2_uxtw): New pattern.
+       (*addsi3_carryin_alt3_uxtw): New pattern.
+       (*add_uxtsi_multp2_uxtw): New pattern.
+       (*subsi3_uxtw): New pattern.
+       (*subsi3_compare0_uxtw): New pattern.
+       (*sub_<shift>_si_uxtw): New pattern.
+       (*sub_mul_imm_si_uxtw): New pattern.
+       (*sub_<optab><SHORT:mode>_si_uxtw): New pattern.
+       (*sub_<optab><SHORT:mode>_shft_si_uxtw): New pattern.
+       (*sub_<optab>si_multp2_uxtw): New pattern.
+       (*sub_uxtsi_multp2_uxtw): New pattern.
+       (*negsi2_uxtw): New pattern.
+       (*negsi2_compare0_uxtw): New pattern.
+       (*neg_<shift>_si2_uxtw): New pattern.
+       (*neg_mul_imm_si2_uxtw): New pattern.
+       (*mulsi3_uxtw): New pattern.
+       (*maddsi_uxtw): New pattern.
+       (*msubsi_uxtw): New pattern.
+       (*mulsi_neg_uxtw): New pattern.
+       (*<su_optab>divsi3_uxtw): New pattern.
+
 2012-12-20  Jakub Jelinek  <jakub@redhat.com>
 
        PR middle-end/55750

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 28f32da..ec65b3c 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1215,6 +1215,22 @@
    (set_attr "mode" "SI")]
 )
 
+;; zero_extend version of above
+(define_insn "*addsi3_aarch64_uxtw"
+  [(set
+    (match_operand:DI 0 "register_operand" "=rk,rk,rk")
+    (zero_extend:DI
+     (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk")
+              (match_operand:SI 2 "aarch64_plus_operand" "I,r,J"))))]
+  ""
+  "@
+  add\\t%w0, %w1, %2
+  add\\t%w0, %w1, %w2
+  sub\\t%w0, %w1, #%n2"
+  [(set_attr "v8type" "alu")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*adddi3_aarch64"
   [(set
     (match_operand:DI 0 "register_operand" "=rk,rk,rk,!w")
@@ -1248,6 +1264,23 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*addsi3_compare0_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+       (compare:CC_NZ
+        (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
+                 (match_operand:SI 2 "aarch64_plus_operand" "rI,J"))
+        (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r,r")
+       (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
+  ""
+  "@
+  adds\\t%w0, %w1, %w2
+  subs\\t%w0, %w1, #%n2"
+  [(set_attr "v8type" "alus")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add<mode>3nr_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
        (compare:CC_NZ
@@ -1284,6 +1317,19 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*add_<shift>_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+        (plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r")
+                            (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+                 (match_operand:SI 3 "register_operand" "r"))))]
+  ""
+  "add\\t%w0, %w3, %w1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add_mul_imm_<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
@@ -1305,6 +1351,18 @@
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*add_<optab><SHORT:mode>_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (plus:SI (ANY_EXTEND:SI (match_operand:SHORT 1 "register_operand" "r"))
+                 (match_operand:GPI 2 "register_operand" "r"))))]
+  ""
+  "add\\t%w0, %w2, %w1, <su>xt<SHORT:size>"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add_<optab><ALLX:mode>_shft_<GPI:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (plus:GPI (ashift:GPI (ANY_EXTEND:GPI
@@ -1317,6 +1375,20 @@
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*add_<optab><SHORT:mode>_shft_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+        (plus:SI (ashift:SI (ANY_EXTEND:SI
+                             (match_operand:SHORT 1 "register_operand" "r"))
+                            (match_operand 2 "aarch64_imm3" "Ui3"))
+                 (match_operand:SI 3 "register_operand" "r"))))]
+  ""
+  "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add_<optab><ALLX:mode>_mult_<GPI:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (plus:GPI (mult:GPI (ANY_EXTEND:GPI
@@ -1329,6 +1401,19 @@
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*add_<optab><SHORT:mode>_mult_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI (plus:SI (mult:SI (ANY_EXTEND:SI
+                            (match_operand:SHORT 1 "register_operand" "r"))
+                           (match_operand 2 "aarch64_pwr_imm3" "Up3"))
+                 (match_operand:SI 3 "register_operand" "r"))))]
+  ""
+  "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add_<optab><mode>_multp2"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (plus:GPI (ANY_EXTRACT:GPI
@@ -1343,6 +1428,22 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*add_<optab>si_multp2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (plus:SI (ANY_EXTRACT:SI
+                  (mult:SI (match_operand:SI 1 "register_operand" "r")
+                           (match_operand 2 "aarch64_pwr_imm3" "Up3"))
+                  (match_operand 3 "const_int_operand" "n")
+                   (const_int 0))
+                 (match_operand:SI 4 "register_operand" "r"))))]
+  "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
+  "add\\t%w0, %w4, %w1, <su>xt%e3 %p2"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add<mode>3_carryin"
   [(set
     (match_operand:GPI 0 "register_operand" "=r")
@@ -1356,6 +1457,21 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*addsi3_carryin_uxtw"
+  [(set
+    (match_operand:DI 0 "register_operand" "=r")
+    (zero_extend:DI
+     (plus:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0))
+             (plus:SI
+              (match_operand:SI 1 "register_operand" "r")
+              (match_operand:SI 2 "register_operand" "r")))))]
+   ""
+   "adc\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "adc")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add<mode>3_carryin_alt1"
   [(set
     (match_operand:GPI 0 "register_operand" "=r")
@@ -1369,6 +1485,21 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*addsi3_carryin_alt1_uxtw"
+  [(set
+    (match_operand:DI 0 "register_operand" "=r")
+    (zero_extend:DI
+     (plus:SI (plus:SI
+              (match_operand:SI 1 "register_operand" "r")
+              (match_operand:SI 2 "register_operand" "r"))
+              (geu:SI (reg:CC CC_REGNUM) (const_int 0)))))]
+   ""
+   "adc\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "adc")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add<mode>3_carryin_alt2"
   [(set
     (match_operand:GPI 0 "register_operand" "=r")
@@ -1382,6 +1513,21 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*addsi3_carryin_alt2_uxtw"
+  [(set
+    (match_operand:DI 0 "register_operand" "=r")
+    (zero_extend:DI
+     (plus:SI (plus:SI
+               (geu:SI (reg:CC CC_REGNUM) (const_int 0))
+              (match_operand:SI 1 "register_operand" "r"))
+             (match_operand:SI 2 "register_operand" "r"))))]
+   ""
+   "adc\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "adc")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add<mode>3_carryin_alt3"
   [(set
     (match_operand:GPI 0 "register_operand" "=r")
@@ -1395,6 +1541,21 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*addsi3_carryin_alt3_uxtw"
+  [(set
+    (match_operand:DI 0 "register_operand" "=r")
+    (zero_extend:DI
+     (plus:SI (plus:SI
+               (geu:SI (reg:CC CC_REGNUM) (const_int 0))
+              (match_operand:SI 2 "register_operand" "r"))
+             (match_operand:SI 1 "register_operand" "r"))))]
+   ""
+   "adc\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "adc")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add_uxt<mode>_multp2"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (plus:GPI (and:GPI
@@ -1411,6 +1572,24 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*add_uxtsi_multp2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (plus:SI (and:SI
+                  (mult:SI (match_operand:SI 1 "register_operand" "r")
+                           (match_operand 2 "aarch64_pwr_imm3" "Up3"))
+                  (match_operand 3 "const_int_operand" "n"))
+                 (match_operand:SI 4 "register_operand" "r"))))]
+  "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0"
+  "*
+  operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
+                                          INTVAL (operands[3])));
+  return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "subsi3"
   [(set (match_operand:SI 0 "register_operand" "=rk")
        (minus:SI (match_operand:SI 1 "register_operand" "r")
@@ -1421,6 +1600,18 @@
    (set_attr "mode" "SI")]
 )
 
+;; zero_extend version of above
+(define_insn "*subsi3_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 1 "register_operand" "r")
+                  (match_operand:SI 2 "register_operand" "r"))))]
+  ""
+  "sub\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "alu")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "subdi3"
   [(set (match_operand:DI 0 "register_operand" "=rk,!w")
        (minus:DI (match_operand:DI 1 "register_operand" "r,!w")
@@ -1448,6 +1639,20 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*subsi3_compare0_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+       (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "r")
+                                (match_operand:SI 2 "register_operand" "r"))
+                      (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))]
+  ""
+  "subs\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "alus")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_<shift>_<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 3 "register_operand" "r")
@@ -1460,6 +1665,20 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*sub_<shift>_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 3 "register_operand" "r")
+                  (ASHIFT:SI
+                   (match_operand:SI 1 "register_operand" "r")
+                   (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))]
+  ""
+  "sub\\t%w0, %w3, %w1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_mul_imm_<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 3 "register_operand" "r")
@@ -1472,6 +1691,20 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*sub_mul_imm_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 3 "register_operand" "r")
+                  (mult:SI
+                   (match_operand:SI 1 "register_operand" "r")
+                   (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
+  ""
+  "sub\\t%w0, %w3, %w1, lsl %p2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 1 "register_operand" "r")
@@ -1483,6 +1716,19 @@
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*sub_<optab><SHORT:mode>_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 1 "register_operand" "r")
+                  (ANY_EXTEND:SI
+                   (match_operand:SHORT 2 "register_operand" "r")))))]
+  ""
+  "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_<optab><ALLX:mode>_shft_<GPI:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 1 "register_operand" "r")
@@ -1495,6 +1741,20 @@
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*sub_<optab><SHORT:mode>_shft_si_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 1 "register_operand" "r")
+                  (ashift:SI (ANY_EXTEND:SI
+                              (match_operand:SHORT 2 "register_operand" "r"))
+                             (match_operand 3 "aarch64_imm3" "Ui3")))))]
+  ""
+  "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_<optab><mode>_multp2"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 4 "register_operand" "r")
@@ -1509,6 +1769,22 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*sub_<optab>si_multp2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 4 "register_operand" "r")
+                  (ANY_EXTRACT:SI
+                   (mult:SI (match_operand:SI 1 "register_operand" "r")
+                            (match_operand 2 "aarch64_pwr_imm3" "Up3"))
+                   (match_operand 3 "const_int_operand" "n")
+                   (const_int 0)))))]
+  "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
+  "sub\\t%w0, %w4, %w1, <su>xt%e3 %p2"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_uxt<mode>_multp2"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 4 "register_operand" "r")
@@ -1525,6 +1801,24 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*sub_uxtsi_multp2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=rk")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 4 "register_operand" "r")
+                  (and:SI
+                   (mult:SI (match_operand:SI 1 "register_operand" "r")
+                            (match_operand 2 "aarch64_pwr_imm3" "Up3"))
+                   (match_operand 3 "const_int_operand" "n")))))]
+  "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0"
+  "*
+  operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
+                                          INTVAL (operands[3])));
+  return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";"
+  [(set_attr "v8type" "alu_ext")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "neg<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (neg:GPI (match_operand:GPI 1 "register_operand" "r")))]
@@ -1534,6 +1828,16 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*negsi2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
+  ""
+  "neg\\t%w0, %w1"
+  [(set_attr "v8type" "alu")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*neg<mode>2_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
        (compare:CC_NZ (neg:GPI (match_operand:GPI 1 "register_operand" "r"))
@@ -1546,6 +1850,19 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*negsi2_compare0_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+       (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "r"))
+                      (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI (neg:SI (match_dup 1))))]
+  ""
+  "negs\\t%w0, %w1"
+  [(set_attr "v8type" "alus")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*neg_<shift>_<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (neg:GPI (ASHIFT:GPI
@@ -1557,6 +1874,19 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*neg_<shift>_si2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (neg:SI (ASHIFT:SI
+                 (match_operand:SI 1 "register_operand" "r")
+                 (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))]
+  ""
+  "neg\\t%w0, %w1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*neg_mul_imm_<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (neg:GPI (mult:GPI
@@ -1568,6 +1898,19 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*neg_mul_imm_si2_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (neg:SI (mult:SI
+                 (match_operand:SI 1 "register_operand" "r")
+                 (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
+  ""
+  "neg\\t%w0, %w1, lsl %p2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "mul<mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (mult:GPI (match_operand:GPI 1 "register_operand" "r")
@@ -1578,6 +1921,18 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*mulsi3_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (mult:SI (match_operand:SI 1 "register_operand" "r")
+                 (match_operand:SI 2 "register_operand" "r"))))]
+  ""
+  "mul\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "mult")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*madd<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
@@ -1589,6 +1944,19 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*maddsi_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+                          (match_operand:SI 2 "register_operand" "r"))
+                 (match_operand:SI 3 "register_operand" "r"))))]
+  ""
+  "madd\\t%w0, %w1, %w2, %w3"
+  [(set_attr "v8type" "madd")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*msub<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (minus:GPI (match_operand:GPI 3 "register_operand" "r")
@@ -1601,6 +1969,20 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*msubsi_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (minus:SI (match_operand:SI 3 "register_operand" "r")
+                  (mult:SI (match_operand:SI 1 "register_operand" "r")
+                           (match_operand:SI 2 "register_operand" "r")))))]
+
+  ""
+  "msub\\t%w0, %w1, %w2, %w3"
+  [(set_attr "v8type" "madd")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*mul<mode>_neg"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (mult:GPI (neg:GPI (match_operand:GPI 1 "register_operand" "r"))
@@ -1612,6 +1994,19 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*mulsi_neg_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (mult:SI (neg:SI (match_operand:SI 1 "register_operand" "r"))
+                 (match_operand:SI 2 "register_operand" "r"))))]
+
+  ""
+  "mneg\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "mult")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "<su_optab>mulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (mult:DI (ANY_EXTEND:DI (match_operand:SI 1 "register_operand" "r"))
@@ -1682,6 +2077,18 @@
    (set_attr "mode" "<MODE>")]
 )
 
+;; zero_extend version of above
+(define_insn "*<su_optab>divsi3_uxtw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (ANY_DIV:SI (match_operand:SI 1 "register_operand" "r")
+                    (match_operand:SI 2 "register_operand" "r"))))]
+  ""
+  "<su>div\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "<su>div")
+   (set_attr "mode" "SI")]
+)
+
 ;; -------------------------------------------------------------------
 ;; Comparison insns
 ;; -------------------------------------------------------------------