arm64: tegra: Add missing CPU PMUs on Tegra186

Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 0c46ab7..a55d7ac 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1534,7 +1534,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               denver_0: cpu@0 {
                        compatible = "nvidia,tegra186-denver";
                        device_type = "cpu";
                        i-cache-size = <0x20000>;
@@ -1547,7 +1547,7 @@
                        reg = <0x000>;
                };
 
-               cpu@1 {
+               denver_1: cpu@1 {
                        compatible = "nvidia,tegra186-denver";
                        device_type = "cpu";
                        i-cache-size = <0x20000>;
@@ -1560,7 +1560,7 @@
                        reg = <0x001>;
                };
 
-               cpu@2 {
+               ca57_0: cpu@2 {
                        compatible = "arm,cortex-a57";
                        device_type = "cpu";
                        i-cache-size = <0xC000>;
@@ -1573,7 +1573,7 @@
                        reg = <0x100>;
                };
 
-               cpu@3 {
+               ca57_1: cpu@3 {
                        compatible = "arm,cortex-a57";
                        device_type = "cpu";
                        i-cache-size = <0xC000>;
@@ -1586,7 +1586,7 @@
                        reg = <0x101>;
                };
 
-               cpu@4 {
+               ca57_2: cpu@4 {
                        compatible = "arm,cortex-a57";
                        device_type = "cpu";
                        i-cache-size = <0xC000>;
@@ -1599,7 +1599,7 @@
                        reg = <0x102>;
                };
 
-               cpu@5 {
+               ca57_3: cpu@5 {
                        compatible = "arm,cortex-a57";
                        device_type = "cpu";
                        i-cache-size = <0xC000>;
@@ -1631,6 +1631,22 @@
                };
        };
 
+       pmu_denver {
+               compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&denver_0 &denver_1>;
+       };
+
+       pmu_a57 {
+               compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
+       };
+
        thermal-zones {
                a57 {
                        polling-delay = <0>;