amd/common: update addrlib for gfx11.5
authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Mon, 18 Sep 2023 19:47:49 +0000 (21:47 +0200)
committerMarge Bot <emma+marge@anholt.net>
Fri, 20 Oct 2023 07:32:34 +0000 (07:32 +0000)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25278>

src/amd/addrlib/src/amdgpu_asic_addr.h
src/amd/addrlib/src/core/addrlib.cpp
src/amd/addrlib/src/gfx11/gfx11addrlib.cpp
src/amd/addrlib/src/gfx11/gfx11addrlib.h

index be3aa8a..ae035fd 100644 (file)
@@ -29,6 +29,7 @@
 #define FAMILY_VGH     0x90 //# 144 / Van Gogh
 #define FAMILY_NV3     0x91 //# 145 / Navi: 3x
 #define FAMILY_GFX1103 0x94
+#define FAMILY_GFX1150 0x96
 #define FAMILY_RMB     0x92 //# 146 / Rembrandt
 #define FAMILY_RPL     0x95 //# 149 / Raphael
 #define FAMILY_MDN     0x97 //# 151 / Mendocino
 #define AMDGPU_GFX1103_R1_RANGE 0x01, 0x80 //# 1 <= x < 128
 #define AMDGPU_GFX1103_R2_RANGE 0x80, 0xFF //# 128 <= x < max
 
+#define AMDGPU_GFX1150_RANGE    0x01, 0xFF //# 1 <= x < max
+
 #define AMDGPU_REMBRANDT_RANGE  0x01, 0xFF //# 01 <= x < 255
 
 #define AMDGPU_RAPHAEL_RANGE    0x01, 0xFF //# 1 <= x < max
 #define ASICREV_IS_NAVI33_P(r)         ASICREV_IS(r, NAVI33)
 #define ASICREV_IS_GFX1103_R1(r)       ASICREV_IS(r, GFX1103_R1)
 #define ASICREV_IS_GFX1103_R2(r)       ASICREV_IS(r, GFX1103_R2)
+#define ASICREV_IS_GFX1150(r)          ASICREV_IS(r, GFX1150)
 
 #define ASICREV_IS_REMBRANDT(r)        ASICREV_IS(r, REMBRANDT)
 
index f0a99b2..407a1b3 100644 (file)
@@ -217,6 +217,7 @@ ADDR_E_RETURNCODE Lib::Create(
                         break;
                     case FAMILY_NV3:
                     case FAMILY_GFX1103:
+                    case FAMILY_GFX1150:
                         pLib = Gfx11HwlInit(&client);
                         break;
                     default:
index a343e56..88b761b 100644 (file)
@@ -739,6 +739,12 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily(
             {
             }
             break;
+        case FAMILY_GFX1150:
+            if (ASICREV_IS_GFX1150(chipRevision))
+            {
+                m_settings.isGfx1150 = 1;
+            }
+            break;
         case FAMILY_GFX1103:
             m_settings.isGfx1103 = 1;
             break;
@@ -1331,6 +1337,7 @@ UINT_32 Gfx11Lib::GetValidDisplaySwizzleModes(
 
         if (false
             || (m_settings.isGfx1103)
+            || (m_settings.isGfx1150)
            )
         {
             // Not all GPUs support displaying with 256kB swizzle modes.
index b67ea72..b07c989 100644 (file)
@@ -34,7 +34,7 @@ struct Gfx11ChipSettings
 {
     struct
     {
-        UINT_32 reserved0           :  1;
+        UINT_32 isGfx1150           :  1;
         UINT_32 isGfx1103           :  1;
         UINT_32 reserved1           : 30;