clk: imx8mn: add clkout1/2 support
authorLucas Stach <l.stach@pengutronix.de>
Mon, 25 Jan 2021 17:41:35 +0000 (18:41 +0100)
committerShawn Guo <shawnguo@kernel.org>
Sat, 30 Jan 2021 13:35:33 +0000 (21:35 +0800)
clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx8mn.c
include/dt-bindings/clock/imx8mn-clock.h

index 3c21db9..324c5fd 100644 (file)
@@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
                                                 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
                                                 "video_pll1_out", "osc_32k", };
 
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+                                          "dummy", "dummy", "gpu_pll_out", "dummy",
+                                          "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+                                          "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
@@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
        hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
        hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
 
+       hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+       hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
+       hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+       hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+       hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
+       hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
        np = dev->of_node;
        base = devm_platform_ioremap_resource(pdev, 0);
        if (WARN_ON(IS_ERR(base))) {
index 621ea0e..d24b627 100644 (file)
 
 #define IMX8MN_CLK_A53_CORE                    214
 
-#define IMX8MN_CLK_END                         215
+#define IMX8MN_CLK_CLKOUT1_SEL                 215
+#define IMX8MN_CLK_CLKOUT1_DIV                 216
+#define IMX8MN_CLK_CLKOUT1                     217
+#define IMX8MN_CLK_CLKOUT2_SEL                 218
+#define IMX8MN_CLK_CLKOUT2_DIV                 219
+#define IMX8MN_CLK_CLKOUT2                     220
+
+#define IMX8MN_CLK_END                         221
 
 #endif