arm: socfpga: Move Stratix10 and Agilex clock manager common code
authorSiew Chin Lim <elly.siew.chin.lim@intel.com>
Wed, 24 Mar 2021 09:16:49 +0000 (17:16 +0800)
committerLey Foon Tan <ley.foon.tan@intel.com>
Thu, 8 Apr 2021 09:29:12 +0000 (17:29 +0800)
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/clock_manager.c
arch/arm/mach-socfpga/clock_manager_agilex.c
arch/arm/mach-socfpga/clock_manager_s10.c
arch/arm/mach-socfpga/include/mach/clock_manager.h
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h

index f0b15f7..be426a5 100644 (file)
@@ -4,12 +4,13 @@
  */
 
 #include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
 #include <command.h>
 #include <init.h>
 #include <wait_bit.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,6 +64,14 @@ int set_cpu_clk_info(void)
        return 0;
 }
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+       return readl(socfpga_get_sysmgr_addr() +
+                    SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
                         char *const argv[])
index 6377f2c..e035c09 100644 (file)
@@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
        return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
 }
 
-u32 cm_get_qspi_controller_clk_hz(void)
-{
-       return readl(socfpga_get_sysmgr_addr() +
-                    SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
 void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10d kHz\n",
index e060e57..4b4f074 100644 (file)
@@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
        return clock;
 }
 
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
-       return readl(socfpga_get_sysmgr_addr() +
-                    SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
 unsigned int cm_get_spi_controller_clk_hz(void)
 {
        u32 clock = cm_get_l3_main_clk_hz();
index 1f734bc..9cf2237 100644 (file)
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
 void cm_wait_for_lock(u32 mask);
 int cm_wait_for_fsm(void);
 void cm_print_clock_quick_summary(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
index 11ddee5..798d374 100644 (file)
@@ -70,8 +70,6 @@ int cm_basic_init(const void *blob);
 unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned long cm_get_mpu_clk_hz(void);
 
-unsigned int cm_get_qspi_controller_clk_hz(void);
-
 #endif /* __ASSEMBLY__ */
 
 #define LOCKED_MASK    (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
index 5c9abe6..4cc1268 100644 (file)
@@ -100,7 +100,6 @@ unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
 unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
 const unsigned int cm_get_osc_clk_hz(const int osc);
 const unsigned int cm_get_f2s_per_ref_clk_hz(void);
index cb7923b..98c3bf1 100644 (file)
@@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
 unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
 
 struct cm_config {